Rev |
Log message |
Author |
Age |
Path |
149 |
Update simulation regression result parser.
Fixed failing SFR test (due to newer MSPGCC version).
Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface) |
olivier.girard |
4343d 08h |
/openmsp430/trunk/core/sim/rtl_sim/run/ |
145 |
Add Dhrystone and CoreMark benchmarks to the simulation environment. |
olivier.girard |
4393d 07h |
/openmsp430/trunk/core/sim/rtl_sim/run/ |
138 |
Update simulation scripts to support Cygwin out of the box for Windows users. |
olivier.girard |
4430d 17h |
/openmsp430/trunk/core/sim/rtl_sim/run/ |
134 |
Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability. |
olivier.girard |
4462d 08h |
/openmsp430/trunk/core/sim/rtl_sim/run/ |
128 |
Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) |
olivier.girard |
4559d 07h |
/openmsp430/trunk/core/sim/rtl_sim/run/ |
122 |
Add coverage report generation (NCVERILOG only)
Add support for the ISIM Xilinx simulator. |
olivier.girard |
4631d 08h |
/openmsp430/trunk/core/sim/rtl_sim/run/ |
111 |
Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly. |
olivier.girard |
4769d 07h |
/openmsp430/trunk/core/sim/rtl_sim/run/ |
106 |
Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution). |
olivier.girard |
4825d 06h |
/openmsp430/trunk/core/sim/rtl_sim/run/ |
91 |
Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface. |
olivier.girard |
4858d 08h |
/openmsp430/trunk/core/sim/rtl_sim/run/ |
76 |
Add possibility to simulate C code within the "core" environment. |
olivier.girard |
4952d 07h |
/openmsp430/trunk/core/sim/rtl_sim/run/ |
73 |
Update all bash scripts headers with "#!/bin/bash" instead of "#!/bin/sh".
This will prevent compatibility problems in systems where bash isn't the default shell. |
olivier.girard |
5059d 09h |
/openmsp430/trunk/core/sim/rtl_sim/run/ |
67 |
Added 16x16 Hardware Multiplier. |
olivier.girard |
5208d 16h |
/openmsp430/trunk/core/sim/rtl_sim/run/ |
65 |
Add possibility to disable waveform dumping by setting the OMSP_NODUMP environment variable to 1. |
olivier.girard |
5219d 06h |
/openmsp430/trunk/core/sim/rtl_sim/run/ |
54 |
Update FPGA projects with the combinatorial loop fixed. |
olivier.girard |
5247d 10h |
/openmsp430/trunk/core/sim/rtl_sim/run/ |
33 |
In order to avoid confusion, the following changes have been implemented to the Verilog code:
- renamed the "rom_*" ports and defines to "pmem_*" (program memory).
- renamed the "ram_*" ports and defines to "dmem_*" (data memory).
In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created. |
olivier.girard |
5276d 10h |
/openmsp430/trunk/core/sim/rtl_sim/run/ |
6 |
Some more SVN ignore properties... |
olivier.girard |
5445d 08h |
/openmsp430/trunk/core/sim/rtl_sim/run/ |
2 |
Upload complete openMSP430 project to the SVN repository |
olivier.girard |
5458d 07h |
/openmsp430/trunk/core/sim/rtl_sim/run/ |