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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [run/] - Rev 99

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Rev Log message Author Age Path
91 Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.		 olivier.girard 4858d 02h /openmsp430/trunk/core/sim/rtl_sim/run/
76 Add possibility to simulate C code within the "core" environment. olivier.girard 4952d 01h /openmsp430/trunk/core/sim/rtl_sim/run/
73 Update all bash scripts headers with "#!/bin/bash" instead of "#!/bin/sh".
This will prevent compatibility problems in systems where bash isn't the default shell.		 olivier.girard 5059d 02h /openmsp430/trunk/core/sim/rtl_sim/run/
67 Added 16x16 Hardware Multiplier. olivier.girard 5208d 10h /openmsp430/trunk/core/sim/rtl_sim/run/
65 Add possibility to disable waveform dumping by setting the OMSP_NODUMP environment variable to 1. olivier.girard 5219d 00h /openmsp430/trunk/core/sim/rtl_sim/run/
54 Update FPGA projects with the combinatorial loop fixed. olivier.girard 5247d 03h /openmsp430/trunk/core/sim/rtl_sim/run/
33 In order to avoid confusion, the following changes have been implemented to the Verilog code:
- renamed the "rom_*" ports and defines to "pmem_*" (program memory).
- renamed the "ram_*" ports and defines to "dmem_*" (data memory).

In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.		 olivier.girard 5276d 03h /openmsp430/trunk/core/sim/rtl_sim/run/
6 Some more SVN ignore properties... olivier.girard 5445d 02h /openmsp430/trunk/core/sim/rtl_sim/run/
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5458d 00h /openmsp430/trunk/core/sim/rtl_sim/run/

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