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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src-c/] - Rev 211

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Rev Log message Author Age Path
211 Add custom printf function to reduce program memory footprint (the TI/RH GCC version is huge). Note that this function was created by DJ Delorie ( http://www.delorie.com/ ) olivier.girard 3126d 03h /openmsp430/trunk/core/sim/rtl_sim/src-c/
202 Add DMA interface support + LINT cleanup olivier.girard 3264d 16h /openmsp430/trunk/core/sim/rtl_sim/src-c/
200 Major verificaiton and benchmark update to support both MSPGCC and RedHat/TI GCC toolchains. olivier.girard 3425d 16h /openmsp430/trunk/core/sim/rtl_sim/src-c/
178 Update all linker scripts with a simplified version.
Thanks to Mihai M. for this one :-)		 olivier.girard 4129d 16h /openmsp430/trunk/core/sim/rtl_sim/src-c/
145 Add Dhrystone and CoreMark benchmarks to the simulation environment. olivier.girard 4391d 17h /openmsp430/trunk/core/sim/rtl_sim/src-c/
142 Beautify the linker script examples. olivier.girard 4412d 17h /openmsp430/trunk/core/sim/rtl_sim/src-c/
141 Update verification environment to support MSPGCC Uniarch (based on GCC 4.5 and later) olivier.girard 4416d 16h /openmsp430/trunk/core/sim/rtl_sim/src-c/
134 Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability.		 olivier.girard 4460d 17h /openmsp430/trunk/core/sim/rtl_sim/src-c/
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4767d 17h /openmsp430/trunk/core/sim/rtl_sim/src-c/
80 Create initial version of the Actel FPGA implementation example. olivier.girard 4934d 00h /openmsp430/trunk/core/sim/rtl_sim/src-c/
76 Add possibility to simulate C code within the "core" environment. olivier.girard 4950d 17h /openmsp430/trunk/core/sim/rtl_sim/src-c/

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