OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src-c/] [sandbox/] - Rev 211

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
211 Add custom printf function to reduce program memory footprint (the TI/RH GCC version is huge). Note that this function was created by DJ Delorie ( http://www.delorie.com/ ) olivier.girard 3119d 21h /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/
202 Add DMA interface support + LINT cleanup olivier.girard 3258d 11h /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/
200 Major verificaiton and benchmark update to support both MSPGCC and RedHat/TI GCC toolchains. olivier.girard 3419d 10h /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/
178 Update all linker scripts with a simplified version.
Thanks to Mihai M. for this one :-)
olivier.girard 4123d 10h /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/
145 Add Dhrystone and CoreMark benchmarks to the simulation environment. olivier.girard 4385d 11h /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/
142 Beautify the linker script examples. olivier.girard 4406d 12h /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/
141 Update verification environment to support MSPGCC Uniarch (based on GCC 4.5 and later) olivier.girard 4410d 11h /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/
134 Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability.
olivier.girard 4454d 12h /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.
olivier.girard 4761d 12h /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/
80 Create initial version of the Actel FPGA implementation example. olivier.girard 4927d 19h /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/
76 Add possibility to simulate C code within the "core" environment. olivier.girard 4944d 11h /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.