OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [synthesis/] - Rev 134

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
134 Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability.
olivier.girard 4462d 00h /openmsp430/trunk/core/synthesis/
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.
olivier.girard 4769d 00h /openmsp430/trunk/core/synthesis/
73 Update all bash scripts headers with "#!/bin/bash" instead of "#!/bin/sh".
This will prevent compatibility problems in systems where bash isn't the default shell.
olivier.girard 5059d 01h /openmsp430/trunk/core/synthesis/
68 Update synthesis scripts with the hardware multiplier support. olivier.girard 5208d 08h /openmsp430/trunk/core/synthesis/
64 Add Actel synthesis environment for size and speed analysis. olivier.girard 5229d 08h /openmsp430/trunk/core/synthesis/
63 Add Altera synthesis environment for size and speed analysis. olivier.girard 5229d 08h /openmsp430/trunk/core/synthesis/
62 Add Xilinx synthesis environment for size&speed analysis. olivier.girard 5229d 10h /openmsp430/trunk/core/synthesis/
56 Update Design Compiler Synthesis scripts. olivier.girard 5246d 04h /openmsp430/trunk/core/synthesis/
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5457d 23h /openmsp430/trunk/core/synthesis/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.