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[/] [openmsp430/] [trunk/] [fpga/] - Rev 158

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Rev	Log message	Author	Age	Path
157	Re-create new LX9 Microboard project to show off the new I2C serial debug interface (and more to come)....	olivier.girard	4247d 16h	/openmsp430/trunk/fpga/
156	Remove current LX9 microboard project (to be replaced with a new one showing off the new I2C based serial debug interface)	olivier.girard	4247d 16h	/openmsp430/trunk/fpga/
155	Update FPGA projects with the latest openMSP430 verilog code.	olivier.girard	4247d 16h	/openmsp430/trunk/fpga/
153	Update XFLOW scripts to bring more automation. Several bitstreams are now checked in for direct use.	olivier.girard	4302d 15h	/openmsp430/trunk/fpga/
151	Add possibility to configure custom Program, Data and Peripheral memory sizes.	olivier.girard	4332d 15h	/openmsp430/trunk/fpga/
149	Update simulation regression result parser. Fixed failing SFR test (due to newer MSPGCC version). Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface)	olivier.girard	4335d 17h	/openmsp430/trunk/fpga/
143	Update FPGA software examples to support MSPGCC Uniarch.	olivier.girard	4406d 17h	/openmsp430/trunk/fpga/
138	Update simulation scripts to support Cygwin out of the box for Windows users.	olivier.girard	4423d 02h	/openmsp430/trunk/fpga/
136	Update all FPGA projects with the latest core version.	olivier.girard	4454d 16h	/openmsp430/trunk/fpga/
132	Update FPGA examples with the POP.B bug fix	olivier.girard	4467d 16h	/openmsp430/trunk/fpga/
128	Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 )	olivier.girard	4551d 16h	/openmsp430/trunk/fpga/
121	Add a new FPGA example for the LX9 Microboard from Avnet. Many thanks to Ricardo Ribalda Delgado for his contribution on this one :-)	olivier.girard	4695d 17h	/openmsp430/trunk/fpga/
112	Modified comment.	olivier.girard	4760d 17h	/openmsp430/trunk/fpga/
111	Re-organized the "openMSP430_defines.v" file. Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning). Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000). As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.	olivier.girard	4761d 17h	/openmsp430/trunk/fpga/
109	Update Xilinx FPGA example with the latest openMSP430 core RTL version.	olivier.girard	4816d 01h	/openmsp430/trunk/fpga/
108	Add serial debug interface tasks to the Actel fpga simulation environment.	olivier.girard	4817d 15h	/openmsp430/trunk/fpga/
107	Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version.	olivier.girard	4817d 15h	/openmsp430/trunk/fpga/
106	Separated the Timer A defines from the openMSP430 ones. Added the "dbg_en" port in order to allow a separate reset of the debug interface. Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped). Renamed "per_wen" to "per_we" to prevent confusion with active low signals. Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).	olivier.girard	4817d 15h	/openmsp430/trunk/fpga/
105	Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions. These were not problematic but this is simply cleaner that way.	olivier.girard	4832d 16h	/openmsp430/trunk/fpga/
104	Update all FPGA example projects with the latest RTL version.	olivier.girard	4836d 17h	/openmsp430/trunk/fpga/

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[/] [openmsp430/] [trunk/] [fpga/] - Rev 158

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