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Rev Log message Author Age Path
79 Fixed retry loop in or_debug_proxy, hopefully more stable when physically resetting the board julius 5180d 08h /openrisc/trunk/
78 Fixed typo in Silos workaround script rherveille 5181d 03h /openrisc/trunk/
77 Added support for Silvaco's Silos simulator
Added workaround for Silos's exit code behaviour		 rherveille 5181d 03h /openrisc/trunk/
76 Added: +libext+.v
Added: +incdir+.		 rherveille 5182d 03h /openrisc/trunk/
75 Fixed toolchain script's cygwin ncurses check julius 5187d 05h /openrisc/trunk/
74 Toolchain script fix for ncurses header checking julius 5205d 08h /openrisc/trunk/
73 toolchain script error fix julius 5205d 09h /openrisc/trunk/
72 Toolchain install script: or1ksim location changed, few tweaks julius 5208d 06h /openrisc/trunk/
71 ORPSoC board builds, adding readmes julius 5224d 13h /openrisc/trunk/
70 ORPSoC cycle accurate trace generation now compatible with latest version of Verilator \(3.800\) - This will break VCD generation on systems which earlier verilator versions\! julius 5228d 17h /openrisc/trunk/
69 ORPSoC xilinx ml501 board update - added ethernet eupport and software test julius 5228d 18h /openrisc/trunk/
68 Fixed up a couple of Makefile things in ORPSoCv2 julius 5231d 10h /openrisc/trunk/
67 New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory julius 5231d 13h /openrisc/trunk/
66 Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software. julius 5251d 11h /openrisc/trunk/
65 ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix julius 5255d 17h /openrisc/trunk/
64 Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile. julius 5258d 12h /openrisc/trunk/
63 Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. julius 5268d 09h /openrisc/trunk/
62 This material is part of the separate website downloads directory. jeremybennett 5279d 12h /openrisc/trunk/
61 The build directory should not be part of the SVN configuration. jeremybennett 5279d 13h /openrisc/trunk/
60 Mark Jarvin's patches to support Mac OS X (Snow Leopard). jeremybennett 5286d 06h /openrisc/trunk/

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