URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [autom4te.cache/] - Rev 510

Rev	Log message	Author	Age	Path
457	or1ksim - couple of ethernet peripheral updates, fixup of ethernet regression test so all tests pass again.	julius	4900d 06h	/openrisc/trunk/or1ksim/autom4te.cache/
442	OR1Ksim - adding trace controlability by SIGUSR1 signal.	julius	4917d 01h	/openrisc/trunk/or1ksim/autom4te.cache/
436	Or1ksim ethernet TAP updates. Ethernet test still failing.	julius	4926d 21h	/openrisc/trunk/or1ksim/autom4te.cache/
428	or1ksim - adding preliminary PHY emulation to ethernet peripheral.	julius	4937d 02h	/openrisc/trunk/or1ksim/autom4te.cache/
418	Or1ksim - adding new option when configuring memories, "exitnops"	julius	4945d 10h	/openrisc/trunk/or1ksim/autom4te.cache/
233	New softfloat FPU and testfloat sw for or1ksim	julius	5045d 22h	/openrisc/trunk/or1ksim/autom4te.cache/
226	Orksim floating point support additions, spr-defs.h updates, newlib cache init routines updated	julius	5049d 04h	/openrisc/trunk/or1ksim/autom4te.cache/
202	Adding executed log in binary format capability to or1ksim	julius	5062d 06h	/openrisc/trunk/or1ksim/autom4te.cache/
60	Mark Jarvin's patches to support Mac OS X (Snow Leopard).	jeremybennett	5268d 06h	/openrisc/trunk/or1ksim/autom4te.cache/
19	Initial commit of Or1ksim 0.3.0 into the new repository	jeremybennett	5480d 13h	/openrisc/trunk/or1ksim/autom4te.cache/