URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] - Rev 47

Rev	Log message	Author	Age	Path
46	debug interfaces now support byte and non-aligned accesses from gdb	julius	5403d 14h	/openrisc/trunk/orpsocv2/bench/
44	New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades	julius	5439d 13h	/openrisc/trunk/orpsocv2/bench/
42	Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model	julius	5479d 07h	/openrisc/trunk/orpsocv2/bench/
40	Added GDB server to verilog simulation via VPI and make target to build and run this model	julius	5483d 14h	/openrisc/trunk/orpsocv2/bench/
6	Checking in ORPSoCv2	julius	5502d 01h	/openrisc/trunk/orpsocv2/bench/