| Rev |
Log message |
Author |
Age |
Path |
| 858 |
orpsoc/tests: Fix or1200-dsxinsn when caches are not present
This test would go into an endless loop when caches are not present. |
stekern |
4099d 09h |
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/ |
| 807 |
ORPSoC: Commit for bug 85 - add DSX support to OR1200.
http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=85
Also added software tests, and added these tests to default regression test list |
julius |
4397d 00h |
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/ |
| 805 |
ORPSoC: Fix for bug 90 - EPCR on range exception bug
http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=90 |
julius |
4397d 00h |
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/ |
| 803 |
ORPSoC: Fix for bug 91, l.sub not setting overflow flag correctly
http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=91 |
julius |
4397d 00h |
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/ |
| 801 |
ORPSoC: Fix bug 88
http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=88 |
julius |
4402d 05h |
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/ |
| 672 |
ORPSoC: Fix Bug 76 - Incorrect unsigned integer less-than compare with COMP3 option enabled
OR1200 RTL fix and software test added. |
julius |
4563d 00h |
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/ |
| 671 |
ORPSoC: Fix for Bug 75 - or1200-except and or1200-ticksyscall regression tests failing due to change in memory model |
julius |
4563d 01h |
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/ |
| 619 |
ORPSoC OR1200 fix and regression test for bug 51.
signed-off Julius Baxter
reviewed by Stefan Kristiansson |
julius |
4695d 02h |
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/ |
| 535 |
ORPSoC - adding sw tests for l.rfe |
julius |
4786d 05h |
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/ |
| 530 |
ORPSoC update
Ethernet MAC Wishbone interface fixes
Beginnings of software update.
ML501 backend script fixes for new ISE |
julius |
4793d 13h |
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/ |
| 506 |
ORPSoC or1200 interrupt and syscall generation test |
julius |
4819d 08h |
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/ |
| 504 |
ORPSoC ALU update with new comparison configuration option, software test for comparisons and register file comment cleanup |
julius |
4836d 04h |
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/ |
| 502 |
ORPSoC update - or1200, ethmac Xilinx fifos
or1200 in ORPSoC has carry bit, overflow bit, and range exception added and tested. New software tests in ORPSoC library. Ml501 build had ethmac fifos added, and or1200_defines updated to use these new or1200 features by default |
julius |
4839d 04h |
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/ |
| 499 |
ORPSoC OR1200 updates - added l.ext instructions with tests, ammended some MAC bugs, decode stage cleanup |
julius |
4841d 01h |
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/ |
| 485 |
ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 |
julius |
4874d 13h |
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/ |
| 477 |
ORPSoC update - Added ability to enable OR1200 caches up to 32KB, which requires line size of 32bytes and 8-beat Wishbone bursts.
Changed cache sizes of both instruction and data cache of reference design to 4kB each. |
julius |
4894d 17h |
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/ |
| 475 |
ORPSoC main simulation makefile tidy up, addition of BSS test to cbasic test, addition or o1ksim config files for each board build, modification of BSS symbols in linker script and crt0. |
julius |
4895d 13h |
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/ |
| 462 |
ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim.
RAM models updated. |
julius |
4902d 16h |
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/ |
| 439 |
ORPSoC update
Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST
Multiply/divide tests for to run on target.
Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.
Added ability to use ram_wb as internal memory on ML501 design.
Fixed ethernet MAC tests for ML501. |
julius |
4934d 08h |
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/ |
| 435 |
ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality. |
julius |
4940d 23h |
/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/ |
