URL https://opencores.org/ocsvn/pairing/pairing/trunk

Subversion Repositories pairing

[/] [pairing/] [trunk/] [rtl/] - Rev 27

Rev	Log message	Author	Age	Path
27	definition for undefined wire	homer.xing	4495d 14h	/pairing/trunk/rtl/
24	LGPL claim in each source hdl file	homer.xing	4509d 10h	/pairing/trunk/rtl/
23	LGPL license text	homer.xing	4509d 11h	/pairing/trunk/rtl/
22	Change TAB to space	homer.xing	4509d 12h	/pairing/trunk/rtl/
17	use logic for $f3m_mux6$	homer.xing	4511d 10h	/pairing/trunk/rtl/
12	Simplify the interface of the core.	homer.xing	4511d 15h	/pairing/trunk/rtl/
11	Cheers! as fast as a rocket	homer.xing	4512d 11h	/pairing/trunk/rtl/
10	Ho ho, better circuit	homer.xing	4513d 05h	/pairing/trunk/rtl/
9	Add constrains file for ISE	homer.xing	4514d 09h	/pairing/trunk/rtl/
8	Finished Tate Pairing. Ha ha ha	homer.xing	4514d 09h	/pairing/trunk/rtl/
7	Finish inversion @ f33m	homer.xing	4522d 14h	/pairing/trunk/rtl/
6	add testbench for $f33m$.	homer.xing	4523d 14h	/pairing/trunk/rtl/
5	rename director : verilog/ -> rtl/	homer.xing	4523d 14h	/pairing/trunk/rtl/
3	finish Duursma Lee algorithm. doing f33m module	homer.xing	4524d 12h	/pairing/trunk/verilog/
2	upload code for Duursma-Lee algorithm. I am still developing them.	homer.xing	4525d 12h	/pairing/trunk/verilog/