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[/] [pdp1/] - Rev 11

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11 Rough xy oscilloscope display program.

Not actually usable, way too slow.
yannv 2613d 18h /pdp1/
10 testtop: use a uart to send serial data yannv 2613d 21h /pdp1/
9 Avoid unsigned port for PC. yannv 2613d 22h /pdp1/
8 Avoid inout signal. yannv 2613d 22h /pdp1/
7 Typo fix. yannv 2613d 22h /pdp1/
6 Modified to use dual-port RAM for scanline buffers, instead of one RAM per scanline.
Note that XST fails to create dual-port RAM if write data on one port is constant!
Next step is to use generic_dpram from opencores common.
yannv 4842d 01h /pdp1/
5 Add _i and _o suffixes to ports. yannv 4842d 03h /pdp1/
4 Filled in some comments in vector2scanline.v.
My very first Verilog module, bear with me.
yannv 4854d 21h /pdp1/
3 Unpacked source code for further development in svn. yannv 4854d 21h /pdp1/
2 Added Mercurial bundle of pre-subversion source code. yannv 4854d 22h /pdp1/
1 The project and the structure was created root 4855d 23h /pdp1/

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