URL https://opencores.org/ocsvn/pit/pit/trunk

Subversion Repositories pit

[/] [pit/] - Rev 17

Rev	Log message	Author	Age	Path
17	Change WISHBONE ack signal so no output is generated when wait states are enabled and the bus transaction is terminated in the first cycle.	rehayes	5246d 07h	/pit/
16	Added master error counter variable, added simulation timout limit	rehayes	5357d 09h	/pit/
15	Fix blocking assigment	rehayes	5385d 10h	/pit/
14	Cosmetic update, changed no-blocking assigment to blocking assigment	rehayes	5454d 08h	/pit/
13	Update to rev 0.3, added SINGLE_CYCLE parameter	rehayes	5484d 12h	/pit/
12	Fixed for single cycle reads	rehayes	5485d 07h	/pit/
11	Changed read task to capture data at rising edge of clock	rehayes	5485d 07h	/pit/
10	Added SINGLE_CYCLE parameter for WISHBONE bus cycles	rehayes	5486d 10h	/pit/
9	fix problem with wb_wacc signal. Old method allowed data to be clocked into register twice.	rehayes	5492d 03h	/pit/
8	Fix ack signal in testbench	rehayes	5492d 04h	/pit/
7	Reflection of minor corrections	rehayes	5496d 09h	/pit/
6	Reflection of minor corrections	rehayes	5496d 09h	/pit/
5		rehayes	5534d 05h	/pit/
4	Initial Release March 14, 2009 - Bob Hayes	rehayes	5534d 06h	/pit/
3	Initial Release March 14, 2009 - Bob Hayes	rehayes	5534d 06h	/pit/
2	Initial Release March 14, 2009 - Bob Hayes	rehayes	5534d 06h	/pit/
1	The project was created and the structure was created	root	5534d 21h	/pit/