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[/] [pit/] [trunk/] - Rev 16

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Rev Log message Author Age Path
16 Added master error counter variable, added simulation timout limit rehayes 5356d 19h /pit/trunk/
15 Fix blocking assigment rehayes 5384d 20h /pit/trunk/
14 Cosmetic update, changed no-blocking assigment to blocking assigment rehayes 5453d 18h /pit/trunk/
13 Update to rev 0.3, added SINGLE_CYCLE parameter rehayes 5483d 21h /pit/trunk/
12 Fixed for single cycle reads rehayes 5484d 16h /pit/trunk/
11 Changed read task to capture data at rising edge of clock rehayes 5484d 17h /pit/trunk/
10 Added SINGLE_CYCLE parameter for WISHBONE bus cycles rehayes 5485d 20h /pit/trunk/
9 fix problem with wb_wacc signal. Old method allowed data to be clocked into register twice. rehayes 5491d 13h /pit/trunk/
8 Fix ack signal in testbench rehayes 5491d 14h /pit/trunk/
7 Reflection of minor corrections rehayes 5495d 19h /pit/trunk/
6 Reflection of minor corrections rehayes 5495d 19h /pit/trunk/
5 rehayes 5533d 15h /pit/trunk/
4 Initial Release March 14, 2009 - Bob Hayes rehayes 5533d 16h /pit/trunk/
3 Initial Release March 14, 2009 - Bob Hayes rehayes 5533d 16h /pit/trunk/
2 Initial Release March 14, 2009 - Bob Hayes rehayes 5533d 16h /pit/trunk/
1 The project was created and the structure was created root 5534d 07h /pit/trunk/

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