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[/] [rtf65002/] - Rev 22

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Rev Log message Author Age Path
22 - fix indirect load robfinch 3913d 02h /rtf65002/
21 - config processor mode on reset
- D flag flags extended precision for add/sub
- added software interrupt call facility
- unimplmented opcode vectoring
- bus error signal support
- merge load states to reduce core size
- zero out ir during interrupt
robfinch 3913d 08h /rtf65002/
20 - greater separation of emulation and native mode in source code
- fix instruction buffer fetch for non-cached accesses
- fix the sta (d),y instruction
robfinch 3914d 14h /rtf65002/
19 - added multibit shifts
- added eight bit CMP instruction
robfinch 3915d 12h /rtf65002/
18 - added shift instruction to assembler
- fixed acouple of minor bugs
robfinch 3915d 12h /rtf65002/
17 - updated docs robfinch 3915d 12h /rtf65002/
16 - tiny basic robfinch 3916d 12h /rtf65002/
15 - updates to assembler
- interrupt support in bootrom.asm
-
robfinch 3916d 12h /rtf65002/
14 - updated docs robfinch 3916d 12h /rtf65002/
13 - fix overflow in immediate mode
- fix bit instruction N,V setting
- add vector base register, modified interrupt vectoring
robfinch 3916d 12h /rtf65002/
12 - added LFSR and TICK count special registers
- added MUL/DIV/MOD instructions
robfinch 3917d 13h /rtf65002/
11 - added bootrom.asm
- fixed bugs in assembler
robfinch 3919d 17h /rtf65002/
10 - fix rind mode in 32 bit mode
- fix flag update in 32 bit mode for RR instructions
- initialize cache tags
- added flag to disable ints until after sp load
robfinch 3919d 18h /rtf65002/
9 updateing docs robfinch 3920d 17h /rtf65002/
8 updateing docs robfinch 3920d 17h /rtf65002/
7 updateing docs robfinch 3920d 17h /rtf65002/
6 setting up project robfinch 3923d 01h /rtf65002/
5 setting up project robfinch 3923d 01h /rtf65002/
4 setting up project robfinch 3923d 01h /rtf65002/
3 setting up project robfinch 3923d 01h /rtf65002/

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