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[/] [rtf65002/] [trunk/] [rtl/] - Rev 33

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Rev Log message Author Age Path
32 - many changes
- new instructions
- code reorganization		 robfinch 3888d 17h /rtf65002/trunk/rtl/
30 - added additional branches
- modified the pc increment
- modified interrupts, all vector through BRK
- registered some decodes
- added SUPPORT macros to allow core trimming		 robfinch 3898d 15h /rtf65002/trunk/rtl/
25 - add EXEC and ATNI instructions
- fix store byte zero page indexed
- fix break instruction		 robfinch 3905d 17h /rtf65002/trunk/rtl/
23 - added subtract immediate from sp
- added stack relative addressing mode
- added move positive, move negative instructions
- fix: TSA instruction		 robfinch 3911d 14h /rtf65002/trunk/rtl/
22 - fix indirect load robfinch 3913d 04h /rtf65002/trunk/rtl/
21 - config processor mode on reset
- D flag flags extended precision for add/sub
- added software interrupt call facility
- unimplmented opcode vectoring
- bus error signal support
- merge load states to reduce core size
- zero out ir during interrupt		 robfinch 3913d 10h /rtf65002/trunk/rtl/
20 - greater separation of emulation and native mode in source code
- fix instruction buffer fetch for non-cached accesses
- fix the sta (d),y instruction		 robfinch 3914d 16h /rtf65002/trunk/rtl/
19 - added multibit shifts
- added eight bit CMP instruction		 robfinch 3915d 14h /rtf65002/trunk/rtl/
13 - fix overflow in immediate mode
- fix bit instruction N,V setting
- add vector base register, modified interrupt vectoring		 robfinch 3916d 14h /rtf65002/trunk/rtl/
12 - added LFSR and TICK count special registers
- added MUL/DIV/MOD instructions		 robfinch 3917d 15h /rtf65002/trunk/rtl/
10 - fix rind mode in 32 bit mode
- fix flag update in 32 bit mode for RR instructions
- initialize cache tags
- added flag to disable ints until after sp load		 robfinch 3919d 19h /rtf65002/trunk/rtl/
5 setting up project robfinch 3923d 03h /rtf65002/trunk/rtl/
2 setting up project robfinch 3923d 03h /rtf65002/trunk/rtl/

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