URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] [sdr_ctrl/] - Rev 66

Rev	Log message	Author	Age	Path
66	dwm tw, bl paramter are passed on the wb2sdrc module	dinesha	4377d 11h	/sdr_ctrl/
65	Updated Log file with CAS latency support 4,5	dinesha	4377d 18h	/sdr_ctrl/
64	CAS Latency support added for 4,5	dinesha	4377d 18h	/sdr_ctrl/
63	FPGA Bench mark results are added	dinesha	4496d 17h	/sdr_ctrl/
62	Synthesis constraint for simplify	dinesha	4496d 18h	/sdr_ctrl/
61	RTL file list are added into SVN	dinesha	4496d 18h	/sdr_ctrl/
60	warning cleanup	dinesha	4496d 18h	/sdr_ctrl/
59	Control path request and data are register now for better FPGA timing	dinesha	4496d 18h	/sdr_ctrl/
58	Read Data is register on RD_FAST=0 case	dinesha	4496d 18h	/sdr_ctrl/
57	Synthesis constraints are added	dinesha	4497d 09h	/sdr_ctrl/
56	FPGA Synth optimisation	dinesha	4497d 10h	/sdr_ctrl/
55	FPGA Synthesis timing optimisation	dinesha	4497d 10h	/sdr_ctrl/
54	FPGA Timing Optimisation	dinesha	4500d 08h	/sdr_ctrl/
53	Test bench upgradation	dinesha	4501d 08h	/sdr_ctrl/
52	Documentation update for request control and transfer control block	dinesha	4501d 08h	/sdr_ctrl/
51	FPGA relating timing optimisation done	dinesha	4501d 09h	/sdr_ctrl/
50	Bug fix the request length is fixe	dinesha	4503d 12h	/sdr_ctrl/
49	clean up	dinesha	4504d 11h	/sdr_ctrl/
48	top-level cleanup	dinesha	4504d 12h	/sdr_ctrl/
47	SDRAM bus converter bug fix and top-level signal clean up	dinesha	4504d 12h	/sdr_ctrl/