URL https://opencores.org/ocsvn/sdram_controller/sdram_controller/trunk

Subversion Repositories sdram_controller

[/] [sdram_controller/] [trunk/] - Rev 12

Rev	Log message	Author	Age	Path
12	1. rolled write recover clocks back to previous value and edited comments 2. increased 200us wait time to 300us in the init module	lynn0p	5356d 18h	/sdram_controller/trunk/
11	consolidated capture into one process and added comments	lynn0p	5357d 14h	/sdram_controller/trunk/
10	Fixes to more glitches uncovered during testing with my T80 SoC. Some ops were getting dropped on the floor when the controller needed to do an auto refresh.	lynn0p	5357d 18h	/sdram_controller/trunk/
9	Got rid of some redundant busy_n <= '0' statements	lynn0p	5359d 06h	/sdram_controller/trunk/
8	Changes made to integrate and test with my homebrew SoC design. 1. One DCM has been removed. Now requires a 100mhz clock fed in. Only consumes one DCM, if you can find a 100mhz clock somewhere. 2. Small timing modifications to fix memory glitches between controller and the t80 soft cpu I'm using.	lynn0p	5359d 06h	/sdram_controller/trunk/
7	Reformatted the comments so they fit in 80 columns	lynn0p	5367d 11h	/sdram_controller/trunk/
6	changes to reduce synthesizer warnings, removed unused signals, etc.	lynn0p	5367d 16h	/sdram_controller/trunk/
5	added header file for ddr.v	lynn0p	5368d 11h	/sdram_controller/trunk/
4	added testbench files to trunk	lynn0p	5368d 11h	/sdram_controller/trunk/
3	adding LGPLv3 license file	lynn0p	5368d 12h	/sdram_controller/trunk/
2	initial checkin	lynn0p	5368d 12h	/sdram_controller/trunk/
1	The project was created and the structure was created	root	5368d 15h	/sdram_controller/trunk/