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[/] [socgen/] - Rev 120

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Rev Log message Author Age Path
120 clean up componentGenerators names and directories
sim + lint now synthesis TestBench
jt_eaton 4245d 23h /socgen/
119 moved copyright files into /verilog
changed cde copyright to apache from gplv3
split out tools into separate subdirectories
changed design.xml files to socgen: namespace
jt_eaton 4280d 17h /socgen/
118 optimized gen_verilog
added padring support
added configuration support
added jtag sims
added accellera candidate bus defs
jt_eaton 4316d 03h /socgen/
117 added yellow pages tools jt_eaton 4343d 21h /socgen/
116 added build_header
now use build_register for all spr components
resynced or1200 code back to use orbuild toolchain
jt_eaton 4378d 19h /socgen/
115 split or1200_cpu up into all ip-xact components
removed dead files
jt_eaton 4422d 23h /socgen/
114 moved or1200 connectivity out of verilog and into ip-xact
added or1200_boot block
removed force of 00 on lowest iwb_addr bits
jt_eaton 4434d 23h /socgen/
113 started refactoring or1200 jt_eaton 4440d 15h /socgen/
112 added more test sims
removed unneeded files
jt_eaton 4450d 04h /socgen/
111 split or1200 out into seperate test suite jt_eaton 4451d 22h /socgen/
110 split out more ip-xact components
added sw sources
jt_eaton 4463d 20h /socgen/
109 removed unused file jt_eaton 4466d 20h /socgen/
108 removed unneeded files jt_eaton 4468d 02h /socgen/
107 added designCfg files to all modules jt_eaton 4468d 05h /socgen/
106 checked in orp_soc project step 2 jt_eaton 4473d 22h /socgen/
105 moved or1200_monitor from testbench to dut jt_eaton 4476d 18h /socgen/
104 fixed search in preprocessor script
added initial orp_soc project
jt_eaton 4478d 19h /socgen/
103 added user guide
resynced to local repository
jt_eaton 4498d 19h /socgen/
102 all ip-xact files now readable by kactus2 jt_eaton 4560d 14h /socgen/
101 Added new designs for minsoc release candidate
convert tool set to parse proper ip-xact

THIS WILL BREAK ALL THE OLD DESIGNS UNTIL I FIX THEIR IP_XACT
jt_eaton 4561d 16h /socgen/

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