URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] - Rev 125

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Rev	Log message	Author	Age	Path
125	Added two new 6502 cores in www.6502.org cleaned up sogen xml files and added module name control	jt_eaton	4126d 09h	/socgen/
124	beta release candidate 1 changed design.xml name aligned schema with filesystem	jt_eaton	4179d 12h	/socgen/
123	added support for ubuntu 12.10	jt_eaton	4194d 05h	/socgen/
122	Moved Nexys2 from opencores.org to digilentinc.com Moved jtag_rpc and or1k Busdefs into cde_jtag and or1200 components	jt_eaton	4202d 07h	/socgen/
121	cleaned up sims, added autogenerated test bench files removed mrisc and experimental or1k code	jt_eaton	4222d 13h	/socgen/
120	clean up componentGenerators names and directories sim + lint now synthesis TestBench	jt_eaton	4240d 14h	/socgen/
119	moved copyright files into /verilog changed cde copyright to apache from gplv3 split out tools into separate subdirectories changed design.xml files to socgen: namespace	jt_eaton	4275d 08h	/socgen/
118	optimized gen_verilog added padring support added configuration support added jtag sims added accellera candidate bus defs	jt_eaton	4310d 17h	/socgen/
117	added yellow pages tools	jt_eaton	4338d 12h	/socgen/
116	added build_header now use build_register for all spr components resynced or1200 code back to use orbuild toolchain	jt_eaton	4373d 09h	/socgen/
115	split or1200_cpu up into all ip-xact components removed dead files	jt_eaton	4417d 14h	/socgen/
114	moved or1200 connectivity out of verilog and into ip-xact added or1200_boot block removed force of 00 on lowest iwb_addr bits	jt_eaton	4429d 13h	/socgen/
113	started refactoring or1200	jt_eaton	4435d 06h	/socgen/
112	added more test sims removed unneeded files	jt_eaton	4444d 18h	/socgen/
111	split or1200 out into seperate test suite	jt_eaton	4446d 13h	/socgen/
110	split out more ip-xact components added sw sources	jt_eaton	4458d 10h	/socgen/
109	removed unused file	jt_eaton	4461d 10h	/socgen/
108	removed unneeded files	jt_eaton	4462d 16h	/socgen/
107	added designCfg files to all modules	jt_eaton	4462d 19h	/socgen/
106	checked in orp_soc project step 2	jt_eaton	4468d 12h	/socgen/

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Subversion Repositories socgen

[/] [socgen/] - Rev 125

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