URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] - Rev 132

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
132	fixed permissions on tools/bin	jt_eaton	3360d 13h	/socgen/trunk/
131	Added elaboration databases and tools Added bus map creation tools	jt_eaton	3360d 14h	/socgen/trunk/
130	Dec 2014 major release trimmed out some IP replaced perl database with Berkeley	jt_eaton	3464d 07h	/socgen/trunk/
129	removed unneeded 6502 files	jt_eaton	3919d 13h	/socgen/trunk/
128	major cleanup added toolflows for sim,syn,documentation,linting and verilog added documentation tools	jt_eaton	3919d 13h	/socgen/trunk/
127	final cleanup before DAC	jt_eaton	4034d 09h	/socgen/trunk/
126	added mor1kx cleanup	jt_eaton	4087d 14h	/socgen/trunk/
125	Added two new 6502 cores in www.6502.org cleaned up sogen xml files and added module name control	jt_eaton	4132d 08h	/socgen/trunk/
124	beta release candidate 1 changed design.xml name aligned schema with filesystem	jt_eaton	4185d 11h	/socgen/trunk/
123	added support for ubuntu 12.10	jt_eaton	4200d 04h	/socgen/trunk/
122	Moved Nexys2 from opencores.org to digilentinc.com Moved jtag_rpc and or1k Busdefs into cde_jtag and or1200 components	jt_eaton	4208d 07h	/socgen/trunk/
121	cleaned up sims, added autogenerated test bench files removed mrisc and experimental or1k code	jt_eaton	4228d 13h	/socgen/trunk/
120	clean up componentGenerators names and directories sim + lint now synthesis TestBench	jt_eaton	4246d 13h	/socgen/trunk/
119	moved copyright files into /verilog changed cde copyright to apache from gplv3 split out tools into separate subdirectories changed design.xml files to socgen: namespace	jt_eaton	4281d 07h	/socgen/trunk/
118	optimized gen_verilog added padring support added configuration support added jtag sims added accellera candidate bus defs	jt_eaton	4316d 16h	/socgen/trunk/
117	added yellow pages tools	jt_eaton	4344d 11h	/socgen/trunk/
116	added build_header now use build_register for all spr components resynced or1200 code back to use orbuild toolchain	jt_eaton	4379d 08h	/socgen/trunk/
115	split or1200_cpu up into all ip-xact components removed dead files	jt_eaton	4423d 13h	/socgen/trunk/
114	moved or1200 connectivity out of verilog and into ip-xact added or1200_boot block removed force of 00 on lowest iwb_addr bits	jt_eaton	4435d 12h	/socgen/trunk/
113	started refactoring or1200	jt_eaton	4441d 05h	/socgen/trunk/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories socgen

[/] [socgen/] [trunk/] - Rev 132

Filtering Options