URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] - Rev 14

Rev	Log message	Author	Age	Path
13	updated for xilinx webpack 11.1	jt_eaton	5179d 16h	/socgen/trunk/
12	switched Makefile to use xilinx 11.1 ise removed timescale from synthesis files now use consist timescale header in all sims	jt_eaton	5180d 03h	/socgen/trunk/
11	moved bsdl files renamed ucf file	jt_eaton	5185d 22h	/socgen/trunk/
10	added impact_bat to generate svf files	jt_eaton	5186d 00h	/socgen/trunk/
9	updated build_cmp and cleaned up fpga script added more utility tools	jt_eaton	5188d 00h	/socgen/trunk/
8	fixed loop sim, now pick up ROM_WORDS from sw dir	jt_eaton	5190d 00h	/socgen/trunk/
7	changed loop to use subroutines fixed typo on variants name	jt_eaton	5191d 00h	/socgen/trunk/
6	added pic_micro from minirisc project with design to run code on a digilent Basys board	jt_eaton	5194d 20h	/socgen/trunk/
5	added testbench and generic clock model	jt_eaton	5196d 01h	/socgen/trunk/
4	added generic model for single ended generic pad	jt_eaton	5196d 01h	/socgen/trunk/
3	started bin and lib directories, added install instructions for ubuntu 9.04	jt_eaton	5196d 15h	/socgen/trunk/
2	added starting docs	jt_eaton	5197d 23h	/socgen/trunk/
1	The project and the structure was created	root	5198d 11h	/socgen/trunk/