URL https://opencores.org/ocsvn/socgen/socgen/trunk

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[/] [socgen/] [trunk/] [tools/] - Rev 117

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Rev	Log message	Author	Age	Path
117	added yellow pages tools	jt_eaton	4344d 05h	/socgen/trunk/tools/
116	added build_header now use build_register for all spr components resynced or1200 code back to use orbuild toolchain	jt_eaton	4379d 02h	/socgen/trunk/tools/
115	split or1200_cpu up into all ip-xact components removed dead files	jt_eaton	4423d 07h	/socgen/trunk/tools/
114	moved or1200 connectivity out of verilog and into ip-xact added or1200_boot block removed force of 00 on lowest iwb_addr bits	jt_eaton	4435d 07h	/socgen/trunk/tools/
113	started refactoring or1200	jt_eaton	4440d 23h	/socgen/trunk/tools/
112	added more test sims removed unneeded files	jt_eaton	4450d 12h	/socgen/trunk/tools/
110	split out more ip-xact components added sw sources	jt_eaton	4464d 04h	/socgen/trunk/tools/
107	added designCfg files to all modules	jt_eaton	4468d 12h	/socgen/trunk/tools/
106	checked in orp_soc project step 2	jt_eaton	4474d 05h	/socgen/trunk/tools/
104	fixed search in preprocessor script added initial orp_soc project	jt_eaton	4479d 02h	/socgen/trunk/tools/
103	added user guide resynced to local repository	jt_eaton	4499d 03h	/socgen/trunk/tools/
101	Added new designs for minsoc release candidate convert tool set to parse proper ip-xact THIS WILL BREAK ALL THE OLD DESIGNS UNTIL I FIX THEIR IP_XACT	jt_eaton	4562d 00h	/socgen/trunk/tools/
100	created workspace prroject=fpga_mrisc for single compile general cleanup	jt_eaton	4574d 08h	/socgen/trunk/tools/
99	moved all projects into /projects/opencores.org added build_register added fizzim	jt_eaton	4617d 00h	/socgen/trunk/tools/
97	changed sim run directory to icarus added ise directory into syn added _tb testbench file to all sims	jt_eaton	4653d 05h	/socgen/trunk/tools/
96	hierConnections now create ports	jt_eaton	4727d 01h	/socgen/trunk/tools/
95	added first cut at busdefs added clock reset enable pads and jtag_rpc	jt_eaton	4735d 23h	/socgen/trunk/tools/
94	socgen now supports both sim and syn views now allow each xml file to set its destination	jt_eaton	4763d 01h	/socgen/trunk/tools/
93	build scripts now support model views linting and coverage starting to work again	jt_eaton	4775d 13h	/socgen/trunk/tools/
92	all testbenchs now built from /sim/xml files bench /models now in Testbench	jt_eaton	4780d 14h	/socgen/trunk/tools/

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[/] [socgen/] [trunk/] [tools/] - Rev 117

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