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[/] [spdif_interface/] [tags/] [rx_beta_1/] [rtl/] - Rev 73

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Rev	Log message	Author	Age	Path
73	New directory structure.	root	5569d 13h	/spdif_interface/tags/rx_beta_1/rtl/
43	This commit was manufactured by cvs2svn to create tag 'rx_beta_1'.		7271d 05h	/spdif_interface/tags/rx_beta_1/rtl/
42	Fixed bug with lock event generation.	gedra	7271d 05h	/spdif_interface/tags/rx_beta_1/rtl/
39	Bug-fix.	gedra	7272d 06h	/spdif_interface/tags/rx_beta_1/rtl/
38	Signal renaming and bug fix.	gedra	7286d 06h	/spdif_interface/tags/rx_beta_1/rtl/
37	Converted to numeric_std and fixed a few bugs.	gedra	7287d 08h	/spdif_interface/tags/rx_beta_1/rtl/
36	Top level entity for receiver.	gedra	7287d 08h	/spdif_interface/tags/rx_beta_1/rtl/
31	Added data output.	gedra	7289d 03h	/spdif_interface/tags/rx_beta_1/rtl/
30	Added Wishbone bus cycle decoder.	gedra	7290d 04h	/spdif_interface/tags/rx_beta_1/rtl/
29	Wishbone bus cycle decoder.	gedra	7290d 04h	/spdif_interface/tags/rx_beta_1/rtl/
28	Delint'ed and changed name of architecture.	gedra	7294d 13h	/spdif_interface/tags/rx_beta_1/rtl/
27	Alternate dual port memory implementation for Altera FPGA's.	gedra	7295d 04h	/spdif_interface/tags/rx_beta_1/rtl/
26	Fixed a few bugs.	gedra	7297d 04h	/spdif_interface/tags/rx_beta_1/rtl/
25	Changed status reg. declaration	gedra	7297d 04h	/spdif_interface/tags/rx_beta_1/rtl/
24	Added channel status decoding.	gedra	7297d 04h	/spdif_interface/tags/rx_beta_1/rtl/
20	Renamed generic and cleaned some lint's	gedra	7300d 04h	/spdif_interface/tags/rx_beta_1/rtl/
19	Added frame decoder and sample extractor	gedra	7300d 04h	/spdif_interface/tags/rx_beta_1/rtl/
18	Frame decoder and sample extractor	gedra	7300d 04h	/spdif_interface/tags/rx_beta_1/rtl/
17	Cleaned up lint warnings.	gedra	7303d 04h	/spdif_interface/tags/rx_beta_1/rtl/
16	Added dual port ram.	gedra	7304d 03h	/spdif_interface/tags/rx_beta_1/rtl/

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Subversion Repositories spdif_interface

[/] [spdif_interface/] [tags/] [rx_beta_1/] [rtl/] - Rev 73

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