URL https://opencores.org/ocsvn/spi/spi/trunk

Subversion Repositories spi

[/] [spi/] [tags/] [rel_7/] [rtl/] [verilog/] - Rev 27

Rev	Log message	Author	Age	Path
27	New directory structure.	root	5568d 07h	/spi/tags/rel_7/rtl/verilog/
24	This commit was manufactured by cvs2svn to create tag 'rel_7'.		7640d 01h	/spi/tags/rel_7/rtl/verilog/
21	Byte selects changed.	simons	7640d 01h	/spi/tags/rel_7/rtl/verilog/
19	Errors fixed.	simons	7641d 05h	/spi/tags/rel_7/rtl/verilog/
17	Define mess fixed.	simons	7644d 02h	/spi/tags/rel_7/rtl/verilog/
15	Defines set in order.	simons	7644d 06h	/spi/tags/rel_7/rtl/verilog/
13	8-bit WB access enabled.	simons	7644d 23h	/spi/tags/rel_7/rtl/verilog/
10	Slave select signal generation bug fixed, default case added when reading registers, to avoid latches.	simons	7683d 06h	/spi/tags/rel_7/rtl/verilog/
9	Support for 128 bits character length added. Zero value divider bug fixed.	simons	7724d 00h	/spi/tags/rel_7/rtl/verilog/
8	Automatic slave select signal generation added.	simons	7744d 01h	/spi/tags/rel_7/rtl/verilog/
7	Support for 64 bit caharacter len added.	simons	7832d 13h	/spi/tags/rel_7/rtl/verilog/
2	Initial import	simons	8031d 01h	/spi/tags/rel_7/rtl/verilog/