URL https://opencores.org/ocsvn/spi/spi/trunk

Subversion Repositories spi

[/] [spi/] [trunk/] [rtl/] [verilog/] - Rev 27

Rev	Log message	Author	Age	Path
27	New directory structure.	root	5570d 18h	/spi/trunk/rtl/verilog/
25	CTRL register bit fields changed, VATS testing support added.	simons	7391d 10h	/spi/trunk/rtl/verilog/
21	Byte selects changed.	simons	7642d 12h	/spi/trunk/rtl/verilog/
19	Errors fixed.	simons	7643d 17h	/spi/trunk/rtl/verilog/
17	Define mess fixed.	simons	7646d 13h	/spi/trunk/rtl/verilog/
15	Defines set in order.	simons	7646d 17h	/spi/trunk/rtl/verilog/
13	8-bit WB access enabled.	simons	7647d 10h	/spi/trunk/rtl/verilog/
10	Slave select signal generation bug fixed, default case added when reading registers, to avoid latches.	simons	7685d 17h	/spi/trunk/rtl/verilog/
9	Support for 128 bits character length added. Zero value divider bug fixed.	simons	7726d 11h	/spi/trunk/rtl/verilog/
8	Automatic slave select signal generation added.	simons	7746d 12h	/spi/trunk/rtl/verilog/
7	Support for 64 bit caharacter len added.	simons	7835d 00h	/spi/trunk/rtl/verilog/
2	Initial import	simons	8033d 12h	/spi/trunk/rtl/verilog/