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[/] [storm_core/] - Rev 20

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Rev Log message Author Age Path
20 - update of data sheet -> note for system memory map layout and d-cache configuration zero_gravity 4513d 21h /storm_core/
19 - simulation test bench added
- example for compatible wishbone fabric/SoC added
- block transfers from user bank updated
zero_gravity 4514d 01h /storm_core/
18 makefile update to ensure no thumb code is generated zero_gravity 4519d 06h /storm_core/
17 small synthesis-friendly update of memory components zero_gravity 4521d 23h /storm_core/
16 WB_TGC(5) signal fixed (indicating instruction/data fetch),
coprocessor read-access bug fixed
zero_gravity 4522d 01h /storm_core/
15 new core version! pipelined wishbone interface, I/D-cache, internal processor timer/lfsr, block transfer instructions, system mode, ... ;) zero_gravity 4522d 06h /storm_core/
14 - corrected stupid error in access arbiter
- updated minor issues
zero_gravity 4660d 02h /storm_core/
13 - corrected endianess converter for memory access
- corrected error in temporal dependence detector
zero_gravity 4660d 22h /storm_core/
12 - corrected error in memory write back interface
- corrected immediate/register offset for byte/halfword memory access
zero_gravity 4661d 03h /storm_core/
11 zero_gravity 4664d 07h /storm_core/
10 New CORE version, ncluding complete system setup with inbuilt memory and wishbone interface.
Ready to execute assembled ARM ASM code, arm-elf-assembler included.
zero_gravity 4664d 08h /storm_core/
9 documentation updated zero_gravity 4754d 05h /storm_core/
8 documentation uploaded ;) zero_gravity 4755d 23h /storm_core/
7 - new register file architecture
- fixed multi-cycle op bug
- architecture update
zero_gravity 4759d 22h /storm_core/
6 new core version - now with arm compatible memory interface zero_gravity 4765d 22h /storm_core/
5 memory interface updated zero_gravity 4816d 21h /storm_core/
4 new instruction cycle controller - interrupt call bug seems to be fixed zero_gravity 4818d 23h /storm_core/
3 zero_gravity 4820d 06h /storm_core/
2 zero_gravity 4832d 07h /storm_core/
1 The project and the structure was created root 4835d 14h /storm_core/

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