URL https://opencores.org/ocsvn/storm_core/storm_core/trunk

Subversion Repositories storm_core

[/] [storm_core/] [trunk/] - Rev 32

Rev	Log message	Author	Age	Path
32	- bug-fix of block transfer operations => now fully ARM-compatible	zero_gravity	4449d 03h	/storm_core/trunk/
31	- small documentary edits - CACHE.vhd modified for better synthesis results - BUS_UNIT.vhd update to fulfill WB specs	zero_gravity	4451d 13h	/storm_core/trunk/
30	- minor edits in doc	zero_gravity	4456d 14h	/storm_core/trunk/
29	- specific IO area is now auto protected - Wishbone compatibility extended - cache flush optimized - accelerated bus cycles due to less overhead	zero_gravity	4457d 14h	/storm_core/trunk/
28	- bugfix in pipeline re-sync of d/i-cache - optimized bus unit - minor edits... ^^	zero_gravity	4468d 17h	/storm_core/trunk/
27	updated "sim" folder - error in testbench environment -> old components -> weren't compatible to new core version anymore => FIXED! ;) - thanks to Pratip Mukherjee	zero_gravity	4472d 16h	/storm_core/trunk/
26	bug fixes: - change in priority for cache miss/dirty/io_access - memory based pc modifications - removed internal timer	zero_gravity	4473d 16h	/storm_core/trunk/
25	bug-fix in cache component: -> error in cache page-access history manager	zero_gravity	4482d 00h	/storm_core/trunk/
24	- changed back to original oc svn folder structure - bug-fix in documentary - WB_ERR_I signal added to terminate wishbone bus access - bug-fix: system mode register set and privs	zero_gravity	4482d 23h	/storm_core/trunk/
23		zero_gravity	4482d 23h	/storm_core/trunk/
22	changed back to original svn folder structure	zero_gravity	4482d 23h	/storm_core/trunk/