URL https://opencores.org/ocsvn/t80/t80/trunk

Subversion Repositories t80

[/] [t80/] [trunk/] [rtl/] [vhdl/] - Rev 47

Rev	Log message	Author	Age	Path
47	New directory structure.	root	5571d 20h	/t80/trunk/rtl/vhdl/
46	Made some bugfixes	andreas	6859d 12h	/t80/trunk/rtl/vhdl/
45	Fixed loopback break generation	jesus	7860d 15h	/t80/trunk/rtl/vhdl/
44	Added some missing features and fixed baud rate generator	jesus	7861d 04h	/t80/trunk/rtl/vhdl/
42	Fixed bus req/ack cycle	jesus	7869d 16h	/t80/trunk/rtl/vhdl/
41	Removed UNISIM library	jesus	7869d 16h	/t80/trunk/rtl/vhdl/
40	Cleanup	jesus	7869d 16h	/t80/trunk/rtl/vhdl/
37	Changed to single register file	jesus	7897d 16h	/t80/trunk/rtl/vhdl/
36	Added component declaration	jesus	7897d 16h	/t80/trunk/rtl/vhdl/
35	Release 0242	jesus	7904d 04h	/t80/trunk/rtl/vhdl/
34	Updated for ISE 5.1	jesus	7904d 09h	/t80/trunk/rtl/vhdl/
29	Fixed (IX/IY+d) timing and added all GB op-codes	jesus	7923d 03h	/t80/trunk/rtl/vhdl/
27	Xilinx SSRAM, initial release	jesus	7924d 03h	/t80/trunk/rtl/vhdl/
26	Fixed instruction timing for POP and DJNZ	jesus	7937d 19h	/t80/trunk/rtl/vhdl/
25	IX/IY timing and ADC/SBC fix	jesus	7939d 05h	/t80/trunk/rtl/vhdl/
24	no message	jesus	7945d 01h	/t80/trunk/rtl/vhdl/
23	Fixed T2Write	jesus	7945d 02h	/t80/trunk/rtl/vhdl/
22	Added 8080 top level	jesus	7945d 02h	/t80/trunk/rtl/vhdl/
20	Updated for new T80s generic	jesus	7950d 01h	/t80/trunk/rtl/vhdl/
19	Initial version	jesus	7950d 01h	/t80/trunk/rtl/vhdl/