URL https://opencores.org/ocsvn/t80/t80/trunk

Subversion Repositories t80

[/] [t80/] [trunk/] [rtl/] [vhdl/] - Rev 29

Rev	Log message	Author	Age	Path
29	Fixed (IX/IY+d) timing and added all GB op-codes	jesus	7923d 11h	/t80/trunk/rtl/vhdl/
27	Xilinx SSRAM, initial release	jesus	7924d 11h	/t80/trunk/rtl/vhdl/
26	Fixed instruction timing for POP and DJNZ	jesus	7938d 03h	/t80/trunk/rtl/vhdl/
25	IX/IY timing and ADC/SBC fix	jesus	7939d 13h	/t80/trunk/rtl/vhdl/
24	no message	jesus	7945d 09h	/t80/trunk/rtl/vhdl/
23	Fixed T2Write	jesus	7945d 10h	/t80/trunk/rtl/vhdl/
22	Added 8080 top level	jesus	7945d 10h	/t80/trunk/rtl/vhdl/
20	Updated for new T80s generic	jesus	7950d 09h	/t80/trunk/rtl/vhdl/
19	Initial version	jesus	7950d 09h	/t80/trunk/rtl/vhdl/
18	Added T2Write generic	jesus	7950d 15h	/t80/trunk/rtl/vhdl/
17	Removed write through	jesus	7952d 08h	/t80/trunk/rtl/vhdl/
16	no message	jesus	7952d 12h	/t80/trunk/rtl/vhdl/
15	Added clock enable and fixed IM 2	jesus	7959d 11h	/t80/trunk/rtl/vhdl/
12	Initial import	jesus	7978d 23h	/t80/trunk/rtl/vhdl/
11	Added support for XST	jesus	7979d 00h	/t80/trunk/rtl/vhdl/
9	Initial import	jesus	7980d 11h	/t80/trunk/rtl/vhdl/
8	Fixed refresh address and DJNZ instruction	jesus	7980d 11h	/t80/trunk/rtl/vhdl/
7	Initial import	jesus	7980d 12h	/t80/trunk/rtl/vhdl/
2	Initial import	jesus	8076d 02h	/t80/trunk/rtl/vhdl/