OpenCores
URL https://opencores.org/ocsvn/tv80/tv80/trunk

Subversion Repositories tv80

[/] [tv80/] - Rev 99

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
99 Fixed setting of flags for LD A, I and LD A, R instructions

Added new testcase ivec_flags to cover new opcodes		 ghutchis 4950d 22h /tv80/
98 Changed malloc for strings with constant length copy, add assertion checks for
null pointers in env memory, and fixed some formatting		 ghutchis 5295d 15h /tv80/
97 Added data in mux, added 16450 UART to environment ghutchis 5299d 18h /tv80/
96 Added Z80 op decode to environment, enabled by -k switch ghutchis 5300d 00h /tv80/
95 Updated regression script to use SystemC simulation ghutchis 5301d 19h /tv80/
94 Ported over env_io.v from Verilog environment to tv_responder.
Basic tests from Verilog environment (hello, fib) now passing in
SystemC environment.		 ghutchis 5303d 20h /tv80/
93 Added common header file for all systemc environment ghutchis 5304d 18h /tv80/
92 Added responder to top level, beginning of support for ihex load ghutchis 5308d 20h /tv80/
91 Preliminary support for SystemC/Verilator environment ghutchis 5308d 22h /tv80/
90 Fixed syntax errors in core preventing Verilator from compiling.
Added new capability to register generator to make registers which
latch on an external event. Removed spurious copyright notice.		 ghutchis 5308d 22h /tv80/
89 RTL and environment fixes for nmi bug ghutchis 5329d 01h /tv80/
88 Fixed bug introduced by conversion of mcycle to one-hot FSM ghutchis 5330d 16h /tv80/
87 Added additional ifdef signals to remove unneede R (refresh) register ghutchis 5345d 23h /tv80/
86 Added old uploaded documents to new repository. root 5569d 05h /tv80/
85 Added old uploaded documents to new repository. root 5569d 11h /tv80/
84 New directory structure. root 5569d 11h /tv80/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.