URL https://opencores.org/ocsvn/tv80/tv80/trunk

Subversion Repositories tv80

[/] [tv80/] [trunk/] [rtl/] - Rev 108

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Rev	Log message	Author	Age	Path
107	Fixed memory contention between config interface and TV80 during write	ghutchis	4860d 22h	/tv80/trunk/rtl/
105	Fixed bugs after environment bringup	ghutchis	4860d 23h	/tv80/trunk/rtl/
103	Updated RTL syntax errors	ghutchis	4861d 05h	/tv80/trunk/rtl/
101	Added sample application for local config processor	ghutchis	4861d 11h	/tv80/trunk/rtl/
100	Changed do to dout in tv80n, checked in fix for flags bug	ghutchis	4892d 09h	/tv80/trunk/rtl/
90	Fixed syntax errors in core preventing Verilator from compiling. Added new capability to register generator to make registers which latch on an external event. Removed spurious copyright notice.	ghutchis	5308d 07h	/tv80/trunk/rtl/
89	RTL and environment fixes for nmi bug	ghutchis	5328d 10h	/tv80/trunk/rtl/
88	Fixed bug introduced by conversion of mcycle to one-hot FSM	ghutchis	5330d 00h	/tv80/trunk/rtl/
87	Added additional ifdef signals to remove unneede R (refresh) register	ghutchis	5345d 08h	/tv80/trunk/rtl/
84	New directory structure.	root	5568d 20h	/tv80/trunk/rtl/
83	Some fixes from Guy-- replace case with casex.	hharte	5642d 02h	/trunk/rtl/
82	Clean up spacing	hharte	5651d 22h	/trunk/rtl/
81	Initial version of TV80 Wishbone Wrapper	hharte	5651d 22h	/trunk/rtl/
80	Misc. code clean-up on mcode to make code smaller and (hopefully) more readable.	ghutchis	6751d 11h	/trunk/rtl/
78	Hajime Ishitani pointed out missing invert on cs_n signal	ghutchis	6794d 12h	/trunk/rtl/
74	Changed default for T2Write to be 1, to match expected behavior for most users.	ghutchis	6905d 13h	/trunk/rtl/
71	Ported UART from T80	ghutchis	6978d 12h	/trunk/rtl/
65	Major restructuring of simple_gmii block. 1) Changed simple_gmii block to simple_gmii_core 2) Migrated RAM instances out of core into top level 3) Removed CPU interface logic and created CPU interface block using register generator 4) Changed status register to interrupt register and added interrupt logic	ghutchis	7037d 08h	/trunk/rtl/
60	Added ifdef TV80_REFRESH, to remove refresh logic by default. Also ran untabify to remove tabs from source code.	ghutchis	7072d 11h	/trunk/rtl/
58	Made TX path async Made TX clock input instead of output	ghutchis	7111d 22h	/trunk/rtl/

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Subversion Repositories tv80

[/] [tv80/] [trunk/] [rtl/] - Rev 108

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