URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [tags/] [rel_1/] [bench/] [verilog/] - Rev 106

Rev	Log message	Author	Age	Path
106	New directory structure.	root	5572d 10h	/uart16550/tags/rel_1/bench/verilog/
78	This commit was manufactured by cvs2svn to create tag 'rel_1'.		8148d 03h	/uart16550/tags/rel_1/bench/verilog/
72	UART PHY added. Files are fully operational, working on HW.	mohor	8173d 11h	/uart16550/tags/rel_1/bench/verilog/
48	Updated specification documentation. Added full 32-bit data bus interface, now as default. Address is 5-bit wide in 32-bit data bus mode. Added wb_sel_i input to the core. It's used in the 32-bit mode. Added debug interface with two 32-bit read-only registers in 32-bit mode. Bits 5 and 6 of LSR are now only cleared on TX FIFO write. My small test bench is modified to work with 32-bit mode.	gorban	8225d 22h	/uart16550/tags/rel_1/bench/verilog/
38	small update to test interrupts	gorban	8252d 02h	/uart16550/tags/rel_1/bench/verilog/
14		gorban	8339d 04h	/uart16550/tags/rel_1/bench/verilog/