URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [tags/] [rel_2/] [rtl/] - Rev 63

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
63	Synplicity was having troubles with the comment.	mohor	8210d 16h	/uart16550/tags/rel_2/rtl/
62	Bug that was entered in the last update fixed (rx state machine).	mohor	8211d 14h	/uart16550/tags/rel_2/rtl/
61	overrun signal was moved to separate block because many sequential lsr reads were preventing data from being written to rx fifo. underrun signal was not used and was removed from the project.	mohor	8212d 09h	/uart16550/tags/rel_2/rtl/
60	Things related to msr register changed. After THRE IRQ occurs, and one character is written to the transmit fifo, the detection of the THRE bit in the LSR is delayed for one character time.	mohor	8212d 13h	/uart16550/tags/rel_2/rtl/
59	MSR register fixed.	mohor	8215d 10h	/uart16550/tags/rel_2/rtl/
58	After reset modem status register MSR should be reset.	mohor	8215d 13h	/uart16550/tags/rel_2/rtl/
57	timeout irq must be set regardless of the rda irq (rda irq does not reset the timeout counter).	mohor	8216d 13h	/uart16550/tags/rel_2/rtl/
56	thre irq should be cleared only when being source of interrupt.	mohor	8216d 13h	/uart16550/tags/rel_2/rtl/
55	some synthesis bugs fixed	gorban	8217d 01h	/uart16550/tags/rel_2/rtl/
54	LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo).	mohor	8217d 14h	/uart16550/tags/rel_2/rtl/
53	Scratch register define added.	mohor	8218d 14h	/uart16550/tags/rel_2/rtl/
52	Scratch register added	gorban	8219d 03h	/uart16550/tags/rel_2/rtl/
51	Igor fixed break condition bugs	gorban	8219d 03h	/uart16550/tags/rel_2/rtl/
50	Bug in LSR[0] is fixed. All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.	gorban	8223d 09h	/uart16550/tags/rel_2/rtl/
49	committed the debug interface file	gorban	8225d 02h	/uart16550/tags/rel_2/rtl/
48	Updated specification documentation. Added full 32-bit data bus interface, now as default. Address is 5-bit wide in 32-bit data bus mode. Added wb_sel_i input to the core. It's used in the 32-bit mode. Added debug interface with two 32-bit read-only registers in 32-bit mode. Bits 5 and 6 of LSR are now only cleared on TX FIFO write. My small test bench is modified to work with 32-bit mode.	gorban	8226d 02h	/uart16550/tags/rel_2/rtl/
47	Fixed: timeout and break didn't pay attention to current data format when counting time	gorban	8231d 04h	/uart16550/tags/rel_2/rtl/
46	Fixed bug that prevented synthesis in uart_receiver.v	gorban	8232d 01h	/uart16550/tags/rel_2/rtl/
45	Lots of fixes: Break condition wasn't handled correctly at all. LSR bits could lose their values. LSR value after reset was wrong. Timing of THRE interrupt signal corrected. LSR bit 0 timing corrected.	gorban	8233d 02h	/uart16550/tags/rel_2/rtl/
44	fixed more typo bugs	gorban	8247d 01h	/uart16550/tags/rel_2/rtl/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories uart16550

[/] [uart16550/] [tags/] [rel_2/] [rtl/] - Rev 63

Filtering Options