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[/] [uart16550/] [tags/] [rel_2/] [rtl/] - Rev 79

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Rev	Log message	Author	Age	Path
79	Bug Fixes: * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. Problem reported by Kenny.Tung. * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. Improvements: * Made FIFO's as general inferrable memory where possible. So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). This saves about 1/3 of the Slice count and reduces P&R and synthesis times. * Added optional baudrate output (baud_o). This is identical to BAUDOUT* signal on 16550 chip. It outputs 16xbit_clock_rate - the divided clock. It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.	gorban	7995d 16h	/uart16550/tags/rel_2/rtl/
75	Endian define added. Big Byte Endian is selected by default.	mohor	8148d 22h	/uart16550/tags/rel_2/rtl/
74	tf_overrun signal was disabled since it was not used	gorban	8153d 23h	/uart16550/tags/rel_2/rtl/
73	major bug in 32-bit mode that prevented register access fixed.	gorban	8160d 22h	/uart16550/tags/rel_2/rtl/
71	Removed confusing comment	gorban	8185d 18h	/uart16550/tags/rel_2/rtl/
70	tf_pop was too wide. Now it is only 1 clk cycle width.	mohor	8191d 03h	/uart16550/tags/rel_2/rtl/
69	More than one character was stored in case of break. End of the break was not detected correctly.	mohor	8199d 18h	/uart16550/tags/rel_2/rtl/
68	lsr[7] was not showing overrun errors.	mohor	8203d 01h	/uart16550/tags/rel_2/rtl/
67	Missing declaration of rf_push_q fixed.	mohor	8210d 01h	/uart16550/tags/rel_2/rtl/
66	rx push changed to be only one cycle wide.	mohor	8210d 01h	/uart16550/tags/rel_2/rtl/
65	Warnings fixed (unused signals removed).	mohor	8211d 06h	/uart16550/tags/rel_2/rtl/
64	Warnings cleared.	mohor	8211d 07h	/uart16550/tags/rel_2/rtl/
63	Synplicity was having troubles with the comment.	mohor	8211d 07h	/uart16550/tags/rel_2/rtl/
62	Bug that was entered in the last update fixed (rx state machine).	mohor	8212d 06h	/uart16550/tags/rel_2/rtl/
61	overrun signal was moved to separate block because many sequential lsr reads were preventing data from being written to rx fifo. underrun signal was not used and was removed from the project.	mohor	8213d 00h	/uart16550/tags/rel_2/rtl/
60	Things related to msr register changed. After THRE IRQ occurs, and one character is written to the transmit fifo, the detection of the THRE bit in the LSR is delayed for one character time.	mohor	8213d 04h	/uart16550/tags/rel_2/rtl/
59	MSR register fixed.	mohor	8216d 01h	/uart16550/tags/rel_2/rtl/
58	After reset modem status register MSR should be reset.	mohor	8216d 04h	/uart16550/tags/rel_2/rtl/
57	timeout irq must be set regardless of the rda irq (rda irq does not reset the timeout counter).	mohor	8217d 04h	/uart16550/tags/rel_2/rtl/
56	thre irq should be cleared only when being source of interrupt.	mohor	8217d 04h	/uart16550/tags/rel_2/rtl/

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[/] [uart16550/] [tags/] [rel_2/] [rtl/] - Rev 79

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