URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [tags/] [rel_2/] [sim/] - Rev 96

Rev	Log message	Author	Age	Path
96	Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead only when TX FIFO is empty. This sauses testcases not to finish.	tadejm	7383d 08h	/uart16550/tags/rel_2/sim/
95	Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead only when TX FIFO is empty. This causes testcases not to finish.	tadejm	7383d 08h	/uart16550/tags/rel_2/sim/
83	Reverted to include uart_defines.v file in other files again.	gorban	7989d 15h	/uart16550/tags/rel_2/sim/
82	Updated to work with latest core.	gorban	7996d 13h	/uart16550/tags/rel_2/sim/
50	Bug in LSR[0] is fixed. All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.	gorban	8224d 22h	/uart16550/tags/rel_2/sim/
48	Updated specification documentation. Added full 32-bit data bus interface, now as default. Address is 5-bit wide in 32-bit data bus mode. Added wb_sel_i input to the core. It's used in the 32-bit mode. Added debug interface with two 32-bit read-only registers in 32-bit mode. Bits 5 and 6 of LSR are now only cleared on TX FIFO write. My small test bench is modified to work with 32-bit mode.	gorban	8227d 15h	/uart16550/tags/rel_2/sim/
17	added empty directories for the required structure.	gorban	8340d 18h	/uart16550/tags/rel_2/sim/
14		gorban	8340d 20h	/uart16550/tags/rel_2/sim/