URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [tags/] [rel_3/] [bench/] - Rev 91

Rev	Log message	Author	Age	Path
91	Removed files due to new complete testbench.	tadejm	7487d 05h	/uart16550/tags/rel_3/bench/
86	restored include for uart_defines.v in uart_test.v	gorban	7932d 12h	/uart16550/tags/rel_3/bench/
83	Reverted to include uart_defines.v file in other files again.	gorban	7979d 03h	/uart16550/tags/rel_3/bench/
72	UART PHY added. Files are fully operational, working on HW.	mohor	8164d 16h	/uart16550/tags/rel_3/bench/
48	Updated specification documentation. Added full 32-bit data bus interface, now as default. Address is 5-bit wide in 32-bit data bus mode. Added wb_sel_i input to the core. It's used in the 32-bit mode. Added debug interface with two 32-bit read-only registers in 32-bit mode. Bits 5 and 6 of LSR are now only cleared on TX FIFO write. My small test bench is modified to work with 32-bit mode.	gorban	8217d 03h	/uart16550/tags/rel_3/bench/
38	small update to test interrupts	gorban	8243d 07h	/uart16550/tags/rel_3/bench/
17	added empty directories for the required structure.	gorban	8330d 06h	/uart16550/tags/rel_3/bench/
14		gorban	8330d 08h	/uart16550/tags/rel_3/bench/