URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [tags/] [rel_3/] [doc/] - Rev 85

Rev	Log message	Author	Age	Path
85	Updated documentation to include latest changes.	gorban	7976d 06h	/uart16550/tags/rel_3/doc/
83	Reverted to include uart_defines.v file in other files again.	gorban	7989d 05h	/uart16550/tags/rel_3/doc/
81	Added lastest additions.	gorban	7996d 03h	/uart16550/tags/rel_3/doc/
48	Updated specification documentation. Added full 32-bit data bus interface, now as default. Address is 5-bit wide in 32-bit data bus mode. Added wb_sel_i input to the core. It's used in the 32-bit mode. Added debug interface with two 32-bit read-only registers in 32-bit mode. Bits 5 and 6 of LSR are now only cleared on TX FIFO write. My small test bench is modified to work with 32-bit mode.	gorban	8227d 05h	/uart16550/tags/rel_3/doc/
20	typo bug fixes	gorban	8332d 07h	/uart16550/tags/rel_3/doc/
14		gorban	8340d 10h	/uart16550/tags/rel_3/doc/