URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [tags/] [rel_3/] [doc/] - Rev 92

Rev	Log message	Author	Age	Path
92	This is revision 1.4, revision 1.5 was put there by mistake.	simons	7486d 13h	/uart16550/tags/rel_3/doc/
90	Add Flextronics header	avisha	7489d 11h	/uart16550/tags/rel_3/doc/
85	Updated documentation to include latest changes.	gorban	7966d 03h	/uart16550/tags/rel_3/doc/
83	Reverted to include uart_defines.v file in other files again.	gorban	7979d 03h	/uart16550/tags/rel_3/doc/
81	Added lastest additions.	gorban	7986d 01h	/uart16550/tags/rel_3/doc/
48	Updated specification documentation. Added full 32-bit data bus interface, now as default. Address is 5-bit wide in 32-bit data bus mode. Added wb_sel_i input to the core. It's used in the 32-bit mode. Added debug interface with two 32-bit read-only registers in 32-bit mode. Bits 5 and 6 of LSR are now only cleared on TX FIFO write. My small test bench is modified to work with 32-bit mode.	gorban	8217d 02h	/uart16550/tags/rel_3/doc/
20	typo bug fixes	gorban	8322d 04h	/uart16550/tags/rel_3/doc/
14		gorban	8330d 08h	/uart16550/tags/rel_3/doc/