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[/] [uart16550/] [tags/] [rel_3/] [rtl/] - Rev 69

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Rev	Log message	Author	Age	Path
69	More than one character was stored in case of break. End of the break was not detected correctly.	mohor	8190d 03h	/uart16550/tags/rel_3/rtl/
68	lsr[7] was not showing overrun errors.	mohor	8193d 11h	/uart16550/tags/rel_3/rtl/
67	Missing declaration of rf_push_q fixed.	mohor	8200d 11h	/uart16550/tags/rel_3/rtl/
66	rx push changed to be only one cycle wide.	mohor	8200d 11h	/uart16550/tags/rel_3/rtl/
65	Warnings fixed (unused signals removed).	mohor	8201d 15h	/uart16550/tags/rel_3/rtl/
64	Warnings cleared.	mohor	8201d 16h	/uart16550/tags/rel_3/rtl/
63	Synplicity was having troubles with the comment.	mohor	8201d 16h	/uart16550/tags/rel_3/rtl/
62	Bug that was entered in the last update fixed (rx state machine).	mohor	8202d 15h	/uart16550/tags/rel_3/rtl/
61	overrun signal was moved to separate block because many sequential lsr reads were preventing data from being written to rx fifo. underrun signal was not used and was removed from the project.	mohor	8203d 09h	/uart16550/tags/rel_3/rtl/
60	Things related to msr register changed. After THRE IRQ occurs, and one character is written to the transmit fifo, the detection of the THRE bit in the LSR is delayed for one character time.	mohor	8203d 14h	/uart16550/tags/rel_3/rtl/
59	MSR register fixed.	mohor	8206d 11h	/uart16550/tags/rel_3/rtl/
58	After reset modem status register MSR should be reset.	mohor	8206d 14h	/uart16550/tags/rel_3/rtl/
57	timeout irq must be set regardless of the rda irq (rda irq does not reset the timeout counter).	mohor	8207d 13h	/uart16550/tags/rel_3/rtl/
56	thre irq should be cleared only when being source of interrupt.	mohor	8207d 14h	/uart16550/tags/rel_3/rtl/
55	some synthesis bugs fixed	gorban	8208d 02h	/uart16550/tags/rel_3/rtl/
54	LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo).	mohor	8208d 15h	/uart16550/tags/rel_3/rtl/
53	Scratch register define added.	mohor	8209d 15h	/uart16550/tags/rel_3/rtl/
52	Scratch register added	gorban	8210d 04h	/uart16550/tags/rel_3/rtl/
51	Igor fixed break condition bugs	gorban	8210d 04h	/uart16550/tags/rel_3/rtl/
50	Bug in LSR[0] is fixed. All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.	gorban	8214d 09h	/uart16550/tags/rel_3/rtl/

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[/] [uart16550/] [tags/] [rel_3/] [rtl/] - Rev 69

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