URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [tags/] [rel_4/] [bench/] - Rev 93

Rev	Log message	Author	Age	Path
93	Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish.	tadejm	7381d 16h	/uart16550/tags/rel_4/bench/
91	Removed files due to new complete testbench.	tadejm	7496d 00h	/uart16550/tags/rel_4/bench/
86	restored include for uart_defines.v in uart_test.v	gorban	7941d 07h	/uart16550/tags/rel_4/bench/
83	Reverted to include uart_defines.v file in other files again.	gorban	7987d 22h	/uart16550/tags/rel_4/bench/
72	UART PHY added. Files are fully operational, working on HW.	mohor	8173d 11h	/uart16550/tags/rel_4/bench/
48	Updated specification documentation. Added full 32-bit data bus interface, now as default. Address is 5-bit wide in 32-bit data bus mode. Added wb_sel_i input to the core. It's used in the 32-bit mode. Added debug interface with two 32-bit read-only registers in 32-bit mode. Bits 5 and 6 of LSR are now only cleared on TX FIFO write. My small test bench is modified to work with 32-bit mode.	gorban	8225d 22h	/uart16550/tags/rel_4/bench/
38	small update to test interrupts	gorban	8252d 02h	/uart16550/tags/rel_4/bench/
17	added empty directories for the required structure.	gorban	8339d 01h	/uart16550/tags/rel_4/bench/
14		gorban	8339d 03h	/uart16550/tags/rel_4/bench/