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[/] [uart16550/] [tags/] [rel_4/] [rtl/] - Rev 68

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Rev	Log message	Author	Age	Path
68	lsr[7] was not showing overrun errors.	mohor	8202d 16h	/uart16550/tags/rel_4/rtl/
67	Missing declaration of rf_push_q fixed.	mohor	8209d 16h	/uart16550/tags/rel_4/rtl/
66	rx push changed to be only one cycle wide.	mohor	8209d 16h	/uart16550/tags/rel_4/rtl/
65	Warnings fixed (unused signals removed).	mohor	8210d 21h	/uart16550/tags/rel_4/rtl/
64	Warnings cleared.	mohor	8210d 21h	/uart16550/tags/rel_4/rtl/
63	Synplicity was having troubles with the comment.	mohor	8210d 22h	/uart16550/tags/rel_4/rtl/
62	Bug that was entered in the last update fixed (rx state machine).	mohor	8211d 20h	/uart16550/tags/rel_4/rtl/
61	overrun signal was moved to separate block because many sequential lsr reads were preventing data from being written to rx fifo. underrun signal was not used and was removed from the project.	mohor	8212d 15h	/uart16550/tags/rel_4/rtl/
60	Things related to msr register changed. After THRE IRQ occurs, and one character is written to the transmit fifo, the detection of the THRE bit in the LSR is delayed for one character time.	mohor	8212d 19h	/uart16550/tags/rel_4/rtl/
59	MSR register fixed.	mohor	8215d 16h	/uart16550/tags/rel_4/rtl/
58	After reset modem status register MSR should be reset.	mohor	8215d 19h	/uart16550/tags/rel_4/rtl/
57	timeout irq must be set regardless of the rda irq (rda irq does not reset the timeout counter).	mohor	8216d 19h	/uart16550/tags/rel_4/rtl/
56	thre irq should be cleared only when being source of interrupt.	mohor	8216d 19h	/uart16550/tags/rel_4/rtl/
55	some synthesis bugs fixed	gorban	8217d 07h	/uart16550/tags/rel_4/rtl/
54	LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo).	mohor	8217d 20h	/uart16550/tags/rel_4/rtl/
53	Scratch register define added.	mohor	8218d 20h	/uart16550/tags/rel_4/rtl/
52	Scratch register added	gorban	8219d 09h	/uart16550/tags/rel_4/rtl/
51	Igor fixed break condition bugs	gorban	8219d 09h	/uart16550/tags/rel_4/rtl/
50	Bug in LSR[0] is fixed. All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.	gorban	8223d 14h	/uart16550/tags/rel_4/rtl/
49	committed the debug interface file	gorban	8225d 08h	/uart16550/tags/rel_4/rtl/

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Subversion Repositories uart16550

[/] [uart16550/] [tags/] [rel_4/] [rtl/] - Rev 68

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