URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [trunk/] [bench/] - Rev 106

Rev	Log message	Author	Age	Path
106	New directory structure.	root	5579d 07h	/uart16550/trunk/bench/
94	Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish.	tadejm	7388d 13h	/trunk/bench/
93	Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish.	tadejm	7388d 13h	/trunk/bench/
91	Removed files due to new complete testbench.	tadejm	7502d 21h	/trunk/bench/
86	restored include for uart_defines.v in uart_test.v	gorban	7948d 05h	/trunk/bench/
83	Reverted to include uart_defines.v file in other files again.	gorban	7994d 20h	/trunk/bench/
72	UART PHY added. Files are fully operational, working on HW.	mohor	8180d 08h	/trunk/bench/
48	Updated specification documentation. Added full 32-bit data bus interface, now as default. Address is 5-bit wide in 32-bit data bus mode. Added wb_sel_i input to the core. It's used in the 32-bit mode. Added debug interface with two 32-bit read-only registers in 32-bit mode. Bits 5 and 6 of LSR are now only cleared on TX FIFO write. My small test bench is modified to work with 32-bit mode.	gorban	8232d 20h	/trunk/bench/
38	small update to test interrupts	gorban	8258d 23h	/trunk/bench/
17	added empty directories for the required structure.	gorban	8345d 22h	/trunk/bench/
14		gorban	8346d 01h	/trunk/bench/