URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [trunk/] [rtl/] - Rev 107

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
106	New directory structure.	root	5572d 03h	/uart16550/trunk/rtl/
105	Timeout interrupt should be generated only when there is at least ony character in the fifo.	igorm	7141d 04h	/trunk/rtl/
103	Brandl Tobias repaired a bug regarding frame error in receiver when brake is received.	tadejm	7297d 22h	/trunk/rtl/
101	Added 2 LSB address generation dependent on select lines and LITLE/BIG endian when UART is in 32-bit mode.	tadejm	7326d 00h	/trunk/rtl/
100	Repaired bug in receiver. When stop bit is sampled and next clock RX input was '0', state machine stayed locked until next '1' which cause loosing at least start bit in case of larger difference of bit times between 2 UARTs.	tadejm	7326d 01h	/trunk/rtl/
99	Added synchronizer flops for RX input.	tadejm	7326d 01h	/trunk/rtl/
98	Added to synchronize RX input to Wishbone clock.	tadejm	7326d 01h	/trunk/rtl/
89	adjusted comment + define	dries	7578d 05h	/trunk/rtl/
88	added clearing the receiver fifo statuses on resets	gorban	7640d 19h	/trunk/rtl/
87	This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended.	gorban	7670d 20h	/trunk/rtl/
84	The uart_defines.v file is included again in sources.	gorban	7987d 16h	/trunk/rtl/
80	Remove uart_fifo.v because it is replaced by other 2 files.	gorban	7994d 14h	/trunk/rtl/
79	Bug Fixes: * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. Problem reported by Kenny.Tung. * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. Improvements: * Made FIFO's as general inferrable memory where possible. So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). This saves about 1/3 of the Slice count and reduces P&R and synthesis times. * Added optional baudrate output (baud_o). This is identical to BAUDOUT* signal on 16550 chip. It outputs 16xbit_clock_rate - the divided clock. It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.	gorban	7994d 14h	/trunk/rtl/
75	Endian define added. Big Byte Endian is selected by default.	mohor	8147d 20h	/trunk/rtl/
74	tf_overrun signal was disabled since it was not used	gorban	8152d 21h	/trunk/rtl/
73	major bug in 32-bit mode that prevented register access fixed.	gorban	8159d 21h	/trunk/rtl/
71	Removed confusing comment	gorban	8184d 17h	/trunk/rtl/
70	tf_pop was too wide. Now it is only 1 clk cycle width.	mohor	8190d 01h	/trunk/rtl/
69	More than one character was stored in case of break. End of the break was not detected correctly.	mohor	8198d 16h	/trunk/rtl/
68	lsr[7] was not showing overrun errors.	mohor	8202d 00h	/trunk/rtl/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories uart16550

[/] [uart16550/] [trunk/] [rtl/] - Rev 107

Filtering Options