URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [trunk/] [rtl/] [verilog/] - Rev 103

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
103	Brandl Tobias repaired a bug regarding frame error in receiver when brake is received.	tadejm	7288d 17h	/uart16550/trunk/rtl/verilog/
101	Added 2 LSB address generation dependent on select lines and LITLE/BIG endian when UART is in 32-bit mode.	tadejm	7316d 19h	/uart16550/trunk/rtl/verilog/
100	Repaired bug in receiver. When stop bit is sampled and next clock RX input was '0', state machine stayed locked until next '1' which cause loosing at least start bit in case of larger difference of bit times between 2 UARTs.	tadejm	7316d 20h	/uart16550/trunk/rtl/verilog/
99	Added synchronizer flops for RX input.	tadejm	7316d 20h	/uart16550/trunk/rtl/verilog/
98	Added to synchronize RX input to Wishbone clock.	tadejm	7316d 20h	/uart16550/trunk/rtl/verilog/
89	adjusted comment + define	dries	7569d 00h	/uart16550/trunk/rtl/verilog/
88	added clearing the receiver fifo statuses on resets	gorban	7631d 13h	/uart16550/trunk/rtl/verilog/
87	This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended.	gorban	7661d 15h	/uart16550/trunk/rtl/verilog/
84	The uart_defines.v file is included again in sources.	gorban	7978d 10h	/uart16550/trunk/rtl/verilog/
80	Remove uart_fifo.v because it is replaced by other 2 files.	gorban	7985d 09h	/uart16550/trunk/rtl/verilog/
79	Bug Fixes: * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. Problem reported by Kenny.Tung. * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. Improvements: * Made FIFO's as general inferrable memory where possible. So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). This saves about 1/3 of the Slice count and reduces P&R and synthesis times. * Added optional baudrate output (baud_o). This is identical to BAUDOUT* signal on 16550 chip. It outputs 16xbit_clock_rate - the divided clock. It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.	gorban	7985d 09h	/uart16550/trunk/rtl/verilog/
75	Endian define added. Big Byte Endian is selected by default.	mohor	8138d 15h	/uart16550/trunk/rtl/verilog/
74	tf_overrun signal was disabled since it was not used	gorban	8143d 16h	/uart16550/trunk/rtl/verilog/
73	major bug in 32-bit mode that prevented register access fixed.	gorban	8150d 15h	/uart16550/trunk/rtl/verilog/
71	Removed confusing comment	gorban	8175d 12h	/uart16550/trunk/rtl/verilog/
70	tf_pop was too wide. Now it is only 1 clk cycle width.	mohor	8180d 20h	/uart16550/trunk/rtl/verilog/
69	More than one character was stored in case of break. End of the break was not detected correctly.	mohor	8189d 11h	/uart16550/trunk/rtl/verilog/
68	lsr[7] was not showing overrun errors.	mohor	8192d 18h	/uart16550/trunk/rtl/verilog/
67	Missing declaration of rf_push_q fixed.	mohor	8199d 18h	/uart16550/trunk/rtl/verilog/
66	rx push changed to be only one cycle wide.	mohor	8199d 18h	/uart16550/trunk/rtl/verilog/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories uart16550

[/] [uart16550/] [trunk/] [rtl/] [verilog/] - Rev 103

Filtering Options