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[/] [uart16550/] [trunk/] [rtl/] [verilog/] - Rev 47

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Rev Log message Author Age Path
47 Fixed: timeout and break didn't pay attention to current data format when counting time gorban 8228d 14h /uart16550/trunk/rtl/verilog/
46 Fixed bug that prevented synthesis in uart_receiver.v gorban 8229d 11h /uart16550/trunk/rtl/verilog/
45 Lots of fixes:
Break condition wasn't handled correctly at all.
LSR bits could lose their values.
LSR value after reset was wrong.
Timing of THRE interrupt signal corrected.
LSR bit 0 timing corrected.		 gorban 8230d 12h /uart16550/trunk/rtl/verilog/
44 fixed more typo bugs gorban 8244d 12h /uart16550/trunk/rtl/verilog/
43 lsr1r error fixed. mohor 8244d 19h /uart16550/trunk/rtl/verilog/
42 ti_int_pnd error fixed. mohor 8244d 19h /uart16550/trunk/rtl/verilog/
41 ti_int_d error fixed. mohor 8244d 19h /uart16550/trunk/rtl/verilog/
40 Synthesis bugs fixed. Some other minor changes gorban 8246d 21h /uart16550/trunk/rtl/verilog/
39 Comments in Slovene language deleted, few small fixes for better work of
old tools. IRQs need to be fix.		 mohor 8248d 19h /uart16550/trunk/rtl/verilog/
37 Heavily rewritten interrupt and LSR subsystems.
Many bugs hopefully squashed.		 gorban 8249d 16h /uart16550/trunk/rtl/verilog/
36 no message mohor 8255d 00h /uart16550/trunk/rtl/verilog/
35 Fixes to break and timeout conditions gorban 8256d 18h /uart16550/trunk/rtl/verilog/
34 fixed parity sending and tx_fifo resets over- and underrun gorban 8258d 17h /uart16550/trunk/rtl/verilog/
33 Small synopsis fixes gorban 8268d 00h /uart16550/trunk/rtl/verilog/
32 Changes data_out to be synchronous again as it should have been. gorban 8268d 17h /uart16550/trunk/rtl/verilog/
31 small fix gorban 8269d 13h /uart16550/trunk/rtl/verilog/
30 Modified port names again gorban 8323d 18h /uart16550/trunk/rtl/verilog/
29 Things connected to parity changed.
Clock devider changed.		 mohor 8324d 13h /uart16550/trunk/rtl/verilog/
28 FIFO was not cleared after the data was read bug fixed. mohor 8325d 01h /uart16550/trunk/rtl/verilog/
27 Stop bit bug fixed.
Parity bug fixed.
WISHBONE read cycle bug fixed,
OE indicator (Overrun Error) bug fixed.
PE indicator (Parity Error) bug fixed.
Register read bug fixed.		 mohor 8325d 17h /uart16550/trunk/rtl/verilog/

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