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[/] [uart16550/] [trunk/] [rtl/] [verilog/] - Rev 50

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Rev	Log message	Author	Age	Path
50	Bug in LSR[0] is fixed. All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.	gorban	8220d 21h	/uart16550/trunk/rtl/verilog/
49	committed the debug interface file	gorban	8222d 15h	/uart16550/trunk/rtl/verilog/
48	Updated specification documentation. Added full 32-bit data bus interface, now as default. Address is 5-bit wide in 32-bit data bus mode. Added wb_sel_i input to the core. It's used in the 32-bit mode. Added debug interface with two 32-bit read-only registers in 32-bit mode. Bits 5 and 6 of LSR are now only cleared on TX FIFO write. My small test bench is modified to work with 32-bit mode.	gorban	8223d 14h	/uart16550/trunk/rtl/verilog/
47	Fixed: timeout and break didn't pay attention to current data format when counting time	gorban	8228d 16h	/uart16550/trunk/rtl/verilog/
46	Fixed bug that prevented synthesis in uart_receiver.v	gorban	8229d 14h	/uart16550/trunk/rtl/verilog/
45	Lots of fixes: Break condition wasn't handled correctly at all. LSR bits could lose their values. LSR value after reset was wrong. Timing of THRE interrupt signal corrected. LSR bit 0 timing corrected.	gorban	8230d 14h	/uart16550/trunk/rtl/verilog/
44	fixed more typo bugs	gorban	8244d 14h	/uart16550/trunk/rtl/verilog/
43	lsr1r error fixed.	mohor	8244d 21h	/uart16550/trunk/rtl/verilog/
42	ti_int_pnd error fixed.	mohor	8244d 21h	/uart16550/trunk/rtl/verilog/
41	ti_int_d error fixed.	mohor	8244d 21h	/uart16550/trunk/rtl/verilog/
40	Synthesis bugs fixed. Some other minor changes	gorban	8246d 23h	/uart16550/trunk/rtl/verilog/
39	Comments in Slovene language deleted, few small fixes for better work of old tools. IRQs need to be fix.	mohor	8248d 21h	/uart16550/trunk/rtl/verilog/
37	Heavily rewritten interrupt and LSR subsystems. Many bugs hopefully squashed.	gorban	8249d 18h	/uart16550/trunk/rtl/verilog/
36	no message	mohor	8255d 02h	/uart16550/trunk/rtl/verilog/
35	Fixes to break and timeout conditions	gorban	8256d 21h	/uart16550/trunk/rtl/verilog/
34	fixed parity sending and tx_fifo resets over- and underrun	gorban	8258d 19h	/uart16550/trunk/rtl/verilog/
33	Small synopsis fixes	gorban	8268d 02h	/uart16550/trunk/rtl/verilog/
32	Changes data_out to be synchronous again as it should have been.	gorban	8268d 20h	/uart16550/trunk/rtl/verilog/
31	small fix	gorban	8269d 15h	/uart16550/trunk/rtl/verilog/
30	Modified port names again	gorban	8323d 20h	/uart16550/trunk/rtl/verilog/

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[/] [uart16550/] [trunk/] [rtl/] [verilog/] - Rev 50

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