URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [trunk/] [rtl/] [verilog/] - Rev 57

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
57	timeout irq must be set regardless of the rda irq (rda irq does not reset the timeout counter).	mohor	8206d 21h	/uart16550/trunk/rtl/verilog/
56	thre irq should be cleared only when being source of interrupt.	mohor	8206d 21h	/uart16550/trunk/rtl/verilog/
55	some synthesis bugs fixed	gorban	8207d 09h	/uart16550/trunk/rtl/verilog/
54	LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo).	mohor	8207d 22h	/uart16550/trunk/rtl/verilog/
53	Scratch register define added.	mohor	8208d 23h	/uart16550/trunk/rtl/verilog/
52	Scratch register added	gorban	8209d 12h	/uart16550/trunk/rtl/verilog/
51	Igor fixed break condition bugs	gorban	8209d 12h	/uart16550/trunk/rtl/verilog/
50	Bug in LSR[0] is fixed. All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.	gorban	8213d 17h	/uart16550/trunk/rtl/verilog/
49	committed the debug interface file	gorban	8215d 10h	/uart16550/trunk/rtl/verilog/
48	Updated specification documentation. Added full 32-bit data bus interface, now as default. Address is 5-bit wide in 32-bit data bus mode. Added wb_sel_i input to the core. It's used in the 32-bit mode. Added debug interface with two 32-bit read-only registers in 32-bit mode. Bits 5 and 6 of LSR are now only cleared on TX FIFO write. My small test bench is modified to work with 32-bit mode.	gorban	8216d 10h	/uart16550/trunk/rtl/verilog/
47	Fixed: timeout and break didn't pay attention to current data format when counting time	gorban	8221d 12h	/uart16550/trunk/rtl/verilog/
46	Fixed bug that prevented synthesis in uart_receiver.v	gorban	8222d 09h	/uart16550/trunk/rtl/verilog/
45	Lots of fixes: Break condition wasn't handled correctly at all. LSR bits could lose their values. LSR value after reset was wrong. Timing of THRE interrupt signal corrected. LSR bit 0 timing corrected.	gorban	8223d 10h	/uart16550/trunk/rtl/verilog/
44	fixed more typo bugs	gorban	8237d 10h	/uart16550/trunk/rtl/verilog/
43	lsr1r error fixed.	mohor	8237d 17h	/uart16550/trunk/rtl/verilog/
42	ti_int_pnd error fixed.	mohor	8237d 17h	/uart16550/trunk/rtl/verilog/
41	ti_int_d error fixed.	mohor	8237d 17h	/uart16550/trunk/rtl/verilog/
40	Synthesis bugs fixed. Some other minor changes	gorban	8239d 19h	/uart16550/trunk/rtl/verilog/
39	Comments in Slovene language deleted, few small fixes for better work of old tools. IRQs need to be fix.	mohor	8241d 17h	/uart16550/trunk/rtl/verilog/
37	Heavily rewritten interrupt and LSR subsystems. Many bugs hopefully squashed.	gorban	8242d 14h	/uart16550/trunk/rtl/verilog/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories uart16550

[/] [uart16550/] [trunk/] [rtl/] [verilog/] - Rev 57

Filtering Options