URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [trunk/] [rtl/] [verilog/] - Rev 67

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
67	Missing declaration of rf_push_q fixed.	mohor	8207d 15h	/uart16550/trunk/rtl/verilog/
66	rx push changed to be only one cycle wide.	mohor	8207d 15h	/uart16550/trunk/rtl/verilog/
65	Warnings fixed (unused signals removed).	mohor	8208d 20h	/uart16550/trunk/rtl/verilog/
64	Warnings cleared.	mohor	8208d 21h	/uart16550/trunk/rtl/verilog/
63	Synplicity was having troubles with the comment.	mohor	8208d 21h	/uart16550/trunk/rtl/verilog/
62	Bug that was entered in the last update fixed (rx state machine).	mohor	8209d 20h	/uart16550/trunk/rtl/verilog/
61	overrun signal was moved to separate block because many sequential lsr reads were preventing data from being written to rx fifo. underrun signal was not used and was removed from the project.	mohor	8210d 14h	/uart16550/trunk/rtl/verilog/
60	Things related to msr register changed. After THRE IRQ occurs, and one character is written to the transmit fifo, the detection of the THRE bit in the LSR is delayed for one character time.	mohor	8210d 19h	/uart16550/trunk/rtl/verilog/
59	MSR register fixed.	mohor	8213d 15h	/uart16550/trunk/rtl/verilog/
58	After reset modem status register MSR should be reset.	mohor	8213d 19h	/uart16550/trunk/rtl/verilog/
57	timeout irq must be set regardless of the rda irq (rda irq does not reset the timeout counter).	mohor	8214d 18h	/uart16550/trunk/rtl/verilog/
56	thre irq should be cleared only when being source of interrupt.	mohor	8214d 19h	/uart16550/trunk/rtl/verilog/
55	some synthesis bugs fixed	gorban	8215d 07h	/uart16550/trunk/rtl/verilog/
54	LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo).	mohor	8215d 20h	/uart16550/trunk/rtl/verilog/
53	Scratch register define added.	mohor	8216d 20h	/uart16550/trunk/rtl/verilog/
52	Scratch register added	gorban	8217d 09h	/uart16550/trunk/rtl/verilog/
51	Igor fixed break condition bugs	gorban	8217d 09h	/uart16550/trunk/rtl/verilog/
50	Bug in LSR[0] is fixed. All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.	gorban	8221d 14h	/uart16550/trunk/rtl/verilog/
49	committed the debug interface file	gorban	8223d 08h	/uart16550/trunk/rtl/verilog/
48	Updated specification documentation. Added full 32-bit data bus interface, now as default. Address is 5-bit wide in 32-bit data bus mode. Added wb_sel_i input to the core. It's used in the 32-bit mode. Added debug interface with two 32-bit read-only registers in 32-bit mode. Bits 5 and 6 of LSR are now only cleared on TX FIFO write. My small test bench is modified to work with 32-bit mode.	gorban	8224d 07h	/uart16550/trunk/rtl/verilog/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories uart16550

[/] [uart16550/] [trunk/] [rtl/] [verilog/] - Rev 67

Filtering Options