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[/] [uart16550/] [trunk/] [rtl/] [verilog/] - Rev 80

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Rev	Log message	Author	Age	Path
80	Remove uart_fifo.v because it is replaced by other 2 files.	gorban	7985d 09h	/uart16550/trunk/rtl/verilog/
79	Bug Fixes: * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. Problem reported by Kenny.Tung. * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. Improvements: * Made FIFO's as general inferrable memory where possible. So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). This saves about 1/3 of the Slice count and reduces P&R and synthesis times. * Added optional baudrate output (baud_o). This is identical to BAUDOUT* signal on 16550 chip. It outputs 16xbit_clock_rate - the divided clock. It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.	gorban	7985d 09h	/uart16550/trunk/rtl/verilog/
75	Endian define added. Big Byte Endian is selected by default.	mohor	8138d 15h	/uart16550/trunk/rtl/verilog/
74	tf_overrun signal was disabled since it was not used	gorban	8143d 16h	/uart16550/trunk/rtl/verilog/
73	major bug in 32-bit mode that prevented register access fixed.	gorban	8150d 15h	/uart16550/trunk/rtl/verilog/
71	Removed confusing comment	gorban	8175d 11h	/uart16550/trunk/rtl/verilog/
70	tf_pop was too wide. Now it is only 1 clk cycle width.	mohor	8180d 20h	/uart16550/trunk/rtl/verilog/
69	More than one character was stored in case of break. End of the break was not detected correctly.	mohor	8189d 11h	/uart16550/trunk/rtl/verilog/
68	lsr[7] was not showing overrun errors.	mohor	8192d 18h	/uart16550/trunk/rtl/verilog/
67	Missing declaration of rf_push_q fixed.	mohor	8199d 18h	/uart16550/trunk/rtl/verilog/
66	rx push changed to be only one cycle wide.	mohor	8199d 18h	/uart16550/trunk/rtl/verilog/
65	Warnings fixed (unused signals removed).	mohor	8200d 23h	/uart16550/trunk/rtl/verilog/
64	Warnings cleared.	mohor	8201d 00h	/uart16550/trunk/rtl/verilog/
63	Synplicity was having troubles with the comment.	mohor	8201d 00h	/uart16550/trunk/rtl/verilog/
62	Bug that was entered in the last update fixed (rx state machine).	mohor	8201d 23h	/uart16550/trunk/rtl/verilog/
61	overrun signal was moved to separate block because many sequential lsr reads were preventing data from being written to rx fifo. underrun signal was not used and was removed from the project.	mohor	8202d 17h	/uart16550/trunk/rtl/verilog/
60	Things related to msr register changed. After THRE IRQ occurs, and one character is written to the transmit fifo, the detection of the THRE bit in the LSR is delayed for one character time.	mohor	8202d 21h	/uart16550/trunk/rtl/verilog/
59	MSR register fixed.	mohor	8205d 18h	/uart16550/trunk/rtl/verilog/
58	After reset modem status register MSR should be reset.	mohor	8205d 21h	/uart16550/trunk/rtl/verilog/
57	timeout irq must be set regardless of the rda irq (rda irq does not reset the timeout counter).	mohor	8206d 21h	/uart16550/trunk/rtl/verilog/

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[/] [uart16550/] [trunk/] [rtl/] [verilog/] - Rev 80

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